Why does Nios® V/g experience data corruption when using DTCM?
Description Due to a problem in Quartus® Prime software, data corruption may occur when running a Nios® V/g processor application that interacts with a Tightly-Coupled Memory (TCM). This happens because of a RTL bug in the load-store unit. This problem is affecting Nios® V/g processor in, Quartus® Prime Pro Edition release 25.3.1 and earlier Quartus® Prime Standard Edition release 25.1 and earlier When Nios® V/g processor executes a non-TCM load (i.e. Load from On-Chip Memory or memory-mapped CSR) followed by a Data TCM load, the latter corrupts the former. This causes the non-TCM load to receive incorrect load data. For example, lw rd1,0(non-TCM) lw rd2,0(TCM) Expectation Actual Failure rd1 = load data from address “non-TCM” rd1 = load data from address “TCM” rd2 = load data from address “TCM“ rd2 = load data from address “TCM“ Resolution This problem is fixed in Quartus® Prime Pro Edition 26.1 and is scheduled to be resolved in a future Quartus® Prime Standard Edition release. Additional Information A patch is available to fix this problem. Quartus® Prime Standard Edition Software v25.1 Patch 0.01 Please contact Altera Support for additional support.Why does the Quartus® Prime Pro fitter fail when compiling the Agilex® 5 GTS HDMI IP Clocked Video design example with the HDMI PHY?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, the fitter may fail during placement when compiling the Agilex® 5 GTS HDMI IP design example configured with the Clocked Video interface with the HDMI PHY configuration. The failure occurs while routing a core global signal for the HDMI receive path and reports that no valid lab location can be found near chip coordinates (157, 74). The fitter then exits unsuccessfully. Resolution This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.Why are Board Test System (BTS) power monitoring readings missing or inaccurate on the Agilex® 5 FPGA E-Series 065B Premium Development Kit?
Description The Board Test System (BTS) does not display power readings for FPGA_VCC_1 and FPGA_VCC_2, and does not report current for VCCO_HVIO when running on the Agilex® 5 FPGA E-Series 065B Premium Development Kit. The issue is observed with BTS software version 1.3.5 and prevents reliable power-estimation analysis. Resolution Update the BTS firmware/software to improve voltage-regulator telemetry and support regulator IOUT, VOUT, and POUT reads through the mailbox interface. Validate the corrected readings for FPGA_VCC_1, FPGA_VCC_2, and VCCO_HVIO across supported board configurations. Additional Information The issue is attributed to a firmware limitation or defect in the BTS voltage-regulator telemetry implementation. Voltage and current values read through I2C may be unstable, inaccurate, or unavailable.Why does lock acquisition fail after dynamic reconfiguration on certain Agilex® 5 FPGA devices?
Description This problem is caused by an error in the Quartus® Post-fit MIF generation flow. Under a specific condition where Dynamic Reconfiguration (DR) is implemented in a Transceiver Bank located on the same side as a downbonded Transceiver Bank, the post-fit flow may generate an incorrect MIF file. This problem is impacted by OPN densities 043, 052, and 065 in the B23A package, and OPN density 160 in the B37A package. Resolution Patches are available to fix this problem for the Quartus Prime Pro Edition Software version 26.1.1 versions. Download and install patch from the following links: Quartus Prime Pro Edition Software v26.1.1 Patch 1.01 This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does Linux fail to access QSPI flash components across all supported devices in the QPDS26.1.1_REL_GSRD_PR release?
Description Due to the change in the default value (from ‘n' to 'y’) of the CONFIG_MTD_SPI_NOR_USE_4K_SECTORS config in Linux from QPDS26.1.1_REL_GSRD_PR release, Linux may fail to access components from the QSPI flash device if the component was built with a configuration using a sector size of 64KB. This may be the case for loading the Linux file system (with jffs or ubi format), which is normally built for a QSPI sector size of 64 KB in Altera binary build recipes. This problem may be observed in any of the Altera SoC devices. Resolution To work around this problem, you need to change the value of the CONFIG_MTD_SPI_NOR_USE_4K_SECTORS config to 'n'. You can do this by adding this line to the arch/arm64/configs/defconfig file: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n You can also override the value of this config as shown next: git clone -b QPDS26.1.1_REL_GSRD_PR https://github.com/altera-fpga/linux-socfpga cd linux-socfpga cat << EOF > config-fragment-agilex5 CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n EOF make defconfig ./scripts/kconfig/merge_config.sh -O ./ ./.config ./config-fragment-agilex5 <continue here the regular Linux build> This problem will be fixed in a future release of Quartus® Prime Pro Edition Software.Why does the Quartus® Prime Pro Edition software version 26.1.1 report Error (25640) when an Agilex® 5 FPGA GTS regional reference clock drives 16 transceiver channels?
Description In the Quartus® Prime Pro Edition software version 26.1, an Agilex® 5 FPGA D-Series transceiver design may compile when a single GTS regional reference-clock pin drives 16 transceiver channels across four GTS quads. Starting with the Quartus Prime Pro Edition software version 26.1.1, the Fitter reports Error (25640) for the reference-clock input. The error indicates that the reference clock drives 16 transceiver channels, exceeding the allowed limit of 12 channels. The same user RTL, SDC, and pin assignments can therefore compile in version 26.1 and fail in version 26.1.1. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I see RRESP=2 if ECC is enabled in External Memory Interfaces (EMIF) IP?
Description When ECC is enabled in External Memory Interfaces (EMIF) IP of Agilex® 7 FPGA M-Series, Agilex® 5 FPGA, and Agilex® 3 FPGA devices, you might receive RRESP=2 during data readback if any of the following conditions is true. DDR4 Component: Data size of the first write command to the associated AXI4 address ≠ 256 bits * N DDR5 Component/DDR5 DIMM/LPDDR4/LPDDR5: Data size of the first write command to the associated AXI4 address ≠ (Channel DQ width * 16) * N where N is a positive integer (1, 2, 3, ...). The hard memory controller uses fixed DQ burst length. The above conditions generate partial access to the memory. The uninitialized portion of data in the memory will cause uncorrectable ECC error, leading to RRESP=2. Below are some example scenarios that showcase this RRESP problem. Example #1: When using a x16+ECC DDR4 Component interface in fabric accessing mode, the first write command to an AXI4 address is a partial access with the use of WSTRB. WDATA width = 256 bits, AWLEN = 0, WSTRB = 0x0000FFFF: Data size of the first write command to the associated AXI4 address = 128 bits Example #2: When using a 1chx32 LPDDR5 interface with in-line ECC enabled in fabric accessing mode, the first write command to an AXI4 address has only one WDATA beat. WDATA width = 256 bits, AWLEN = 0: Data size of the first write command to the associated AXI4 address = 256 bits Channel DQ width * 16 = 512 bits Example #3: When using a x32+ECC DDR5 RDIMM interface in 256-bit NoC accessing mode, the first write command to an AXI4 address uses an even number AWLEN value. WDATA width = 256 bits, AWLEN = 2: Data size of the first write command to the associated AXI4 address = 768 bits Channel DQ width * 16 = 512 bits Resolution To work around this problem, ensure the data size of the first write command to the associated AXI4 address equals to either 256 bits * N or (Channel DQ width * 16) * N, depending on the memory protocol. An alternative method is available starting with Quartus® Prime Pro Edition Software version 26.1.1. When IP parameter Initialize Memory in the Advanced Calibration Settings section is enabled, on calibration passing, and before handing off control of the memory to user logic, the memory will be initialized with all zeros in the data section and the corresponding ECC codes in the ECC section. With this approach, there is no special requirement on the data size of the first write command to the associated AXI4 address. Note: To avoid leading to long simulation time, only the first 256 bytes of memory will be initialized in simulation when Initialize Memory is enabled. Additional Information DDR4 DIMM interface and LPDDR5 interface using link ECC are not affected by this RRESP problem.Error message received from device : Internal error. (subcode 0x001A, Info 0x00000000, Location 0x0000701D )
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, you might encounter this error while configuring new signed and encrypted Partial Reconfiguration (PR) persona bitstreams. The problem impacts Agilex® 5 FPGA PR designs enabled for Encryption and Authentication. Resolution This problem will be fixed in a future release of Quartus® Prime Pro Edition Software. No fix is planned in Quartus® Prime Pro Edition Software version 26.1.1. If you encounter this problem, file a ticket through Altera Premier Support (APS) system to requuest a software patch.Error(24244): Found an error when generating the IBIS Output File for board analysis. Refer to "<project_directory>/output_files/xxx.log" for more information
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you mat see this error when using the EDA Netlist Writer to generate an IBIS Model. This problem occurs when the project includes R-tile or P-tile I/O pins. Resolution This problem has been fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software.Why is the bus ordering reversed in the Technology Map Viewer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see that the bus ordering is reversed in the Technology Map Viewer. This problem occurs when a design contains a Block Design File (BDF) whose output bus is connected to a SystemVerilog HDL packed array from a top-level SystemVerilog HDL module. For example, the expected mapping in the Technology Map Viewer is: inst0 -> Out[0] inst1 -> Out[1] inst2 -> Out[2] inst3 -> Out[3] However, the actual mapping after compilation in the Technology Map Viewer become: inst0 -> Out[3] inst1 -> Out[2] inst2 -> Out[1] inst3 -> Out[0] Resolution To work around this problem, do one of the following: Convert the BDF file to Verilog HDL or VHDL. Open the BDF file in the Quartus® Prime Standard Edition Software. Select File > Create / Update > Create HDL Design File from Current File. Choose Verilog HDL or VHDL. Replace the original BDF module in the Quartus® Prime Pro Edition Software project with the generated HDL file. Explicitly reorder the bits in the top-level SystemVerilog HDL module by using a SystemVerilog HDL streaming operator in the port connection.