Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer?
Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does U-Boot fail to boot from SD Card in SD High-Speed mode in Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is different than 200 MHz in release 26.1?
Description Due to the default SD Combo Phy timing parameters assigned in the U-Boot device tree (socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex5_socdk_013b-u-boot.dtsi ) for release 26.1, U-Boot may fail to boot from the SD Card in SD-HS mode on Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is not 200 MHz (i.e. using 50 MHz). The problem lies in the fact that those default parameters are calculated using a soft PHY clock default value of 200 MHz, but the required timing parameters may differ for any other frequencies. This problem is observed mainly when the U-Boot FSBL fails to load the u-boot.itb from the SD Card, but it may also be observed when U-Boot SSBL fails to load Linux* from the SD Card. Resolution To workaround this problem, you need to enable a tuning mechanism from within the Cadence SDHCI driver by applying the attached U-Boot patch (enable_hs_tuning.patch). This tuning mechanism consists of a runtime calibration process to find the optimal data sampling point. The conditions in which this mechanism is active are: The boot device is a SD Card (no eMMC) The operation mode is SD-HS cdns,sd-hs-tuning parameter is enabled in the device tree The CONFIG_MMC_SUPPORTS_TUNING config is enabled The attached enable_hs_tuning.patch lists the updates needed to enable the tuning mechanism for a 50 MHz SOFT PHY clock. This is a temporary workaround that you could use until a proper software fix gets released. Note: The patch provided is for the Agilex® 5 DK-A5E013BM16AEA development kit (using socfpga_agilex5_socdk_013b-u-boot.dtsi). For other Agilex® 5 or Agilex® 3 FPGA production development kits, the patch solution is the same, users are recommended to apply the updates to the respective device tree file ( i.e. socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex3_socdk-u-boot.dtsi). The source code to support the tuning mechanism will be included in a future release.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1?
Description The latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1 can be downloaded from the following links. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 1.33fw: Fixed race condition in handling SHA isr and resumption of FPGA data blocks.Drain DMA post a configuration/PR to flush out left over data if any. Firmware version 1.22fw: Enabled 85 Ohm Rx Termination for PCIe designs. Resolved problem related to Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT having link up issue Resolved problem related to IEEE 802.3-2022 50GBASE-KR compliance testing marginality during Link Training (LT). Resolved problem related to FGT transceivers using certain FGT Attribute Access method sequence hanging. Firmware version 1.15fw: Added Safe SEU error injection mailbox command. Please also see the following links: Updating the SDM Firmware in the Agilex® FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.Synthesis Critical Violation: IPC-40026 - System clock frequency mismatch
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, there will be a critical synthesis violation when using Agilex® 5 GTS SDI II IP with BASE and PHY mode, and set System PLL frequency to a value other than 700MHz. Resolution You can ignore this violation if the System PLL output frequency meets the minimum requirement in Table 25 of the GTS SDI II IP User Guide: SDI Mode Minimum System PLL Output Frequency HD-SDI single rate 150 MHz 3G-SDI single rate 300 MHz Triple rate SDI (up to 3G-SDI) 300 MHz Multi rate SDI (up to 12G-SDI) 600 MHz This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration?
Description In Agilex® 5 FPGA and Agilex® 3 FPGA devices that include transceivers, if the board connect the power to GTS transceiver bank and RCOMP pin left unconnected (regardless the design include a transceiver or not), while the HVIO pin is configured as input or bidirectional, high‑voltage I/O (HVIO) pins in a specific HVIO bank may fail to function after device configuration. The pins may appear stuck at high, not respond to user logic, or not transition to the expected I/O behavior. This issue does not affect the device configuration process and the device can enter user mode. This issue affects the HVIO bank adjacent to a GTS transceiver bank and is related to specific power and pin connection conditions during board design. Add the content of the new article or describe the problem or bug. Due to a product architecture requirement in Agilex® 5 FPGA and Agilex® 3 FPGA devices with GTS transceivers, the HVIO pins in the affected bank are not configured correctly during device configuration when the following pin connection condition exists. This issue occurs when ALL of the following are true: The RCOMP_GTS pin is left floating on the affected side AND The corresponding GTS transceiver power supply pins for that entire side are powered (not tied to GND): VCCEHT_GTS connected to 1.8 V VCCERT_GTS connected to 1.0 V Under this condition, all HVIO pins in the HVIO bank adjacent to that GTS transceiver bank may appear non‑functional after configuration. Note: This issue does not occur when the RCOMP_GTS pin is properly terminated with a 499 Ω resistor. Resolution The RCOMP_GTS pin may only be left floating if the GTS transceiver power supply pins for the entire side are tied to GND. To avoid this issue, implement one of the following supported configurations: Option 1 (Recommended): Connect the corresponding RCOMP_GTS pin to a 499 Ω resistor. Option 2: Tie all GTS transceiver power supply pins on that side (VCCEHT_GTS and VCCERT_GTS) to GND, if transceivers on that side are not used. Additional Information Refer to the updated guidelines for Agilex 5: Pin Connection Guidelines for Agilex® 5 FPGAs and SoCs (Updated in April 2026). Related Articles Why does the high-voltage I/O (HVIO) input pin stuck at high in Agilex™ 5 FPGA devices? | Altera Community - 338218Fatal Error: hipi_ok, BSYN_QI_LABMGR::sync_lchip_lab + fitter_bsyn
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you might encounter this error while compiling a Partial Reconfiguration (PR) Implementation Revision design. Resolution This problem will be fixed in Quartus® Prime Pro Edition Software version 26.1.1 release onwards. No fix is planned in Quartus® Prime Pro Edition Software version 26.1. If you encounter this Quartus IE, file a service ticket through Altera Premier Support (APS) system for a software patch.