Why does the Simulation Library Compiler fail due to a missing km_220model.sv file in Quartus® Prime Pro Edition 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, the Simulation Library Compiler might fail when compiling simulation libraries for a supported third-party simulator (for example Aldec Riviera-PRO*, Siemens EDA QuestaSim*, or Cadence Xcelium*) if you compile libraries using RTL-only or Compatible Mode for Quartus simulation flow without selecting a specific device family. The compile might stop with an error that a simulation source file such as km_220model.sv cannot be found under the Quartus installation quartus/eda/sim_lib directory. Example errors: Cannot find source file: <Quartus installation>/quartus/eda/sim_lib/km_220model.sv Failed to open design unit file km_220model.sv in read mode. This occurs because the Simulation Library Compiler requests certain simulation model files that are not included in the Quartus® Prime Pro Edition software version 26.1 installer. Those model files are not required to simulate designs that target currently supported device families. Libraries that already compiled successfully before the error remain valid. Refer to the Quartus Prime Pro Edition User Guide: Third-party Simulation (document ID: 683870). Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 26.1, follow these steps: Open a command prompt or terminal where the Quartus Prime software and your simulator license are available. Re-run the Simulation Library Compiler and specify your target device family with the -family option. Do not use an RTL-only compile that omits -family when you only need libraries for one device family. Example (Aldec Riviera-PRO, Verilog, Quartus-compatible mode): quartus_sh --simlib_comp -tool rivierapro -language verilog -mode quartus -family "Arria 10" -tool_path <path_to_riviera_bin> -directory <output_directory> Replace Arria® 10 FPGA with your device family name. Run quartus_sh --help=simlib_comp to list valid -family values for your install. Alternatively, in the Quartus Prime software GUI: Click Tools > Launch Simulation Library Compiler. Select your simulation tool, HDL language, target device family, and output location. Start Compilation. If you must keep an RTL-only or all-library compile on version 26.1 only: Create an empty placeholder file named km_220model.sv in <Quartus installation>/quartus/eda/sim_lib/. Re-run the Simulation Library Compiler. If the compile reports another missing file under sim_lib with a similar name pattern, create an empty placeholder for that file and continue. This problem is fixed in the Quartus® Prime Pro Edition Software version 26.3.Why does Test Engine driver synchronization fail when Memory AXI4 drivers use different clock frequencies?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 26.1 and earlier, Driver Synchronization between Test Engine Memory AXI4 drivers does not work correctly when the drivers use different clock frequencies. When using post and wait commands across drivers with different clock frequencies, you may observe one of the following behaviors: A post command from a slower driver causes the faster driver to skip multiple wait commands. A post command from a faster driver causes the slower driver to hang and fail to continue from the wait command. Traffic patterns that do not use post or wait commands are not affected. Resolution There is no workaround for this problem. Use Driver Synchronization only when all synchronized drivers use the same clock frequency.Why am I seeing Synopsys VCSMX simulation failure using GTS SDI II Revision B Silicon Design Example ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, this problem is caused by incorrect atom parameter settings in the dynamic reconfiguration design example, resulting in Synopsys VCSMX simulation failures. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does the simulation of my Altera® AXI BFMs fail?
Description In the Quartus® Prime Pro Edition Software, a VHDL testbench generated by Visual Designer Studio or Platform Designer using Altera® AXI BFM will error out. The Altera AXI BFMs only support testbenches generated in Verilog HDL or System Verilog HDL. In the Siemens* Questa* Simulator, the error message may be similar to this: ** Error: <file name>.vhd: (vcom-1598) Library "<library name>" not found. Resolution To avoid this problem, generate the testbench in Verilog HDL or System Verilog HDL.Why is Agilex® 5 FPGA HPS IP's Auto-Place IP failed to place the selected peripheral after Apply Selections ?
Description When assigning peripherals to the HPS IO, you may encounter a placement limitation due to the peripheral cannot fit into the available unused IO locations. The error message is not displayed in the Parameterization Messages but appears in the Messages window after running Auto-Place IP. This snapshot is an example: Resolution This problem is plan to be fix in Quartus® Prime Pro Edition Software v26.1.Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Is my Development Cable affected by this? If your USB Blaster III Development cable has a serial number ranging from UB3000000 - UB3006090, then you will need to update the PID. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration?
Description HVIO PLL reconfiguration may require word-addressed register offsets for Agilex® 5 FPGA and Agilex® 3 FPGA devices. The HVIO PLL reconfiguration registers for Agilex 5 and Agilex 3 devices are documented using byte offsets, but the Avalon® Memory‑Mapped (Avalon‑MM) interface expects word-addressed offsets. Using the documented byte offsets directly on the address bus can cause incorrect register access, which prevents the PLL from recovering after it loses lock during reconfiguration. Resolution Apply the following workaround to ensure correct HVIO PLL reconfiguration: Use word-addressed offsets when accessing HVIO PLL registers through the Avalon-MM interface. Convert documented byte offsets to word offsets by dividing by 4 before driving the address bus. Update the register address mapping in your design accordingly. Example: localparam [8:0] ENABLE_RW_ADDR = 9'h10 >> 2; // 0x04 localparam [8:0] ENABLE_RECAL_ADDR = 9'h48 >> 2; // 0x12 localparam [8:0] CLK_GATING_ADDR = 9'h54 >> 2; // 0x15 localparam [8:0] CLEAR_STATUS_ADDR = 9'h58 >> 2; // 0x16 localparam [8:0] C0_ADDR = 9'h5C >> 2; // 0x17 localparam [8:0] C1_ADDR = 9'h60 >> 2; // 0x18 localparam [8:0] RESET_ADDR = 9'h80 >> 2; // 0x20 localparam [8:0] RECAL_ADDR = 9'h88 >> 2; // 0x22Internal Error: Sub-system: RTM, File: /quartus/tsm/rtm/rtm_min_cost_flow_retimer.cpp, Line: 3097 Cost-scaling is not supported yet.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you may see the this internal error during the Fitter stage. Resolution To work around this problem, disable the Early Retimer by adding this QSF assignment: set_global_assignment -name FITTER_EARLY_RETIMING OFF This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.
