Why does the Synchronous FIFO Parameterizable Macro (sync_fifo) incorrectly output all zeroes data after being empty?

Description

Due to a problem in the Quartus^® Prime Pro Edition Software version 25.3.1 or earlier, you might see that the first output data from the FIFO after the FIFO has been empty is incorrectly set to zero. This problem occurs when using the Synchronous FIFO Parameterizable Macro (sync_fifo) in show-ahead mode.

 

Resolution

To work around this problem, instantiate the FIFO FPGA IP instead of the Synchronous FIFO Parameterizable Macro.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.