Why does U-Boot initially read incorrect information from the EMIF controller Read-Only registers, but later retrieve the correct information on Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices in Quartus® Prime Pro edition software 26.1.1 and earlier?

Description

Due to a synchronization issue between U-Boot and the IOSSM firmware, U-Boot may read incorrect values from EMIF controller read-only registers, such as MAILBOX_HEADER and MEM_TOTAL_CAPACITY_INTF. This occurs when U-Boot accesses these registers before the IOSSM firmware has completed their initialization. Once the IOSSM firmware initializes the registers, subsequent reads return the correct values.

This issue is observed in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices when using Quartus® Prime Pro Edition Software version 26.1.1 and earlier releases.

Resolution

A permanent fix is planned for a future release and will include the following enhancements:

1. The IOSSM firmware will set the MB_READY bit (bit 31) in the MAILBOX_HEADER register of the EMIF Controller to 1, indicating that the read-only registers have been fully initialized.
2. U-Boot will poll the MB_READY bit in the MAILBOX_HEADER register and wait for it to be asserted before reading any other read-only registers in the EMIF Controller. This behavior will be enabled only when the CONFIG_IO96B_MB_READY Kconfig option is selected. To maintain compatibility with earlier IOSSM firmware versions that do not support the MB_READY bit, the CONFIG_IO96B_MB_READY option will be disabled by default.