Why does U-Boot initially read incorrect information from the EMIF controller Read-Only registers, but later retrieve the correct information on Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices in Quartus® Prime Pro edition software 26.1.1 and earlier?
Description Due to a synchronization issue between U-Boot and the IOSSM firmware, U-Boot may read incorrect values from EMIF controller read-only registers, such as MAILBOX_HEADER and MEM_TOTAL_CAPACITY_INTF. This occurs when U-Boot accesses these registers before the IOSSM firmware has completed their initialization. Once the IOSSM firmware initializes the registers, subsequent reads return the correct values. This issue is observed in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices when using Quartus® Prime Pro Edition Software version 26.1.1 and earlier releases. Resolution A permanent fix is planned for a future release and will include the following enhancements: The IOSSM firmware will set the MB_READY bit (bit 31) in the MAILBOX_HEADER register of the EMIF Controller to 1, indicating that the read-only registers have been fully initialized. U-Boot will poll the MB_READY bit in the MAILBOX_HEADER register and wait for it to be asserted before reading any other read-only registers in the EMIF Controller. This behavior will be enabled only when the CONFIG_IO96B_MB_READY Kconfig option is selected. To maintain compatibility with earlier IOSSM firmware versions that do not support the MB_READY bit, the CONFIG_IO96B_MB_READY option will be disabled by default.Why does the Agilex® 7 FPGA HPS EMIF and fabric EMIF hang after core reconfiguration when both interfaces share the same IO bank in x72 configuration?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when Agilex® 7 FPGA F-Series and I-Series HPS EMIF and fabric EMIF share the same IO bank in x72 configuration and the design operates in HPS-first mode, the initial configuration can succeed, but subsequent core reconfigurations can cause the fabric EMIF calibration firmware to hang for designs targeting in Agilex® 7 FPGA F-Series and I-Series devices. The observed failure signature is that, after the FPGA is reconfigured without a full board power cycle, the fabric EMIF no longer responds correctly and the calibration flow does not assert cal_success or cal_fail. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.2. Download and install patch 0.70fw below. quartus-24.2-0.70fw-linux.zip quartus-24.2-0.70fw-readme.zip quartus-24.2-0.70fw-windows.zip A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 25.1.1. Download and install patch 1.54fw below. quartus-25.1.1-1.54fw-linux.zip quartus-25.1.1-1.54fw-readme.zip quartus-25.1.1-1.54fw-windows.zip This problem is resolved in Quartus® Prime Pro Edition Software version 26.1.1.Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices. Resolution This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.Why does the AXI ready signal assert when EMIF calibration fails in Quartus® Prime Pro Edition 25.1.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the AXI ready signal might assert when EMIF calibration fails for designs targeting Agilex® 5 FPGA E-series devices using the EMIF IP. The AXI ready signal is asserted as expected when calibration passes, but it is also asserted unexpectedly when calibration fails. This behavior can confuse users into thinking the AXI bus is ready to access even though calibration was not successful. Resolution This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the slew rate value become unset after upgrading External Memory Interfaces (EMIF) IP in Agilex® 7 FPGA F-Series and I-Series devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, the slew rate values in the FPGA I/O tab of External Memory Interfaces (EMIF) IP might change to unset after upgrading the IP to a newer version. Resolution To work around this problem, follow these steps: Toggle the Use default I/O settings checkbox. Change slew rate to desired settings. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1.
Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column
Description The following fitter error may be seen in a project implementing two independent External Memory Interfaces Cyclone®10 DDR3 IP placed in I/O banks in the same I/O column which are sharing a reset signal connected to their global_reset_n ports but not sharing clocks : Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. The following conflicting signals were found: Info(18087): Signal: <emif_0_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int Info(18087): Signal: <emif_1_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int In this configuration, the DDR3 IP global_reset_n ports must be connected to the same reset signal. Note that DDR3 clock sharing (pll reference clock or core clocks) is optional. Resolution To work around this fitter error: Ensure that the Cyclone® 10 DDR3 IP parameter Diagnostics > Example Design > Enable In-System-Sources-and-Probes (ISSP) is not selected. If there is an ISSP assignment in the project .qsf file as shown below, comment it out or delete it. set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1" The enabling of ISSP in a project causes the DDR3 IP reset signals to be interpreted by the Quartus® Prime Pro Edition Software as being different, even though they are connected to the same signal source.Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905
Description When targeting the Arria® 10 DDR4 IP and running the EMIF Toolkit in the Quartus® Prime Pro Software versions 19.2 or earlier, you may see the errors below. Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905 interface_id < EMITT_NF_EMIF_131_MAX_NUM_MEM_INTERFACES Stack Trace: 0xe3bae: EMITT_HARDWARE_READER_NF_EMIF_131::load_param_tables 0x71e (sld_emitt) 0xe1d24: EMITT_HARDWARE_READER_NF_EMIF_131::establish_connection 0x254 (sld_emitt) 0x5eb5e: emitt_establish_connection 0x31e (sld_emitt) ... End-trace Resolution To work around this problem, set the Interface ID parameter (in the Calibration Debug Options under the Diagnostics tab of the DDR4 IP) to a value equal to 10 or less. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why does the Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Quartus Prime Pro Edition Software version 19.4 and later.How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller?
Description Due to a problem in the Intel® Stratix® 10 MX HBM2 controller when using the Intel Quartus® Prime Pro Edition software versions 20.4 or earlier, you may see that the AXI master returns a different value for the read address ID axi_0_0_rid signal if the read burst length axi_0_0_arlen signal is greater than 2. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 20.4 or earlier, Download hbm_burst_rid_fix.zip file and replace the following encrypted files from the existing ones. ./sim_mentor/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_191/sim/mentor/ ./syn_quartus/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_19 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.