Does the Agilex™ 5/3 FPGA HPS EMIF support the External Memory Interface Debug Toolkit?
Description The HPS EMIF controller does support the External Memory Interface Debug Toolkit. Using the following steps, create a design that instantiates the FPGA memory controller using the parameters for the HPS memory interface, and route it to the same I/O that the HPS EMIF uses. Related Information 12.5. Debugging with the External Memory Interface Debug Toolkit 1. Select the HPS EMIF IP within the Platform Designer project. 2. Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS IP window. 3. In the new window, single-click on the EMIF IP inside the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design. 4. Select the directory for the compile design: 5. The example design will be created. NOTE: If the HPS-EMIF is composed of 2 fabric-EMIFs, then the generated example design will only contain 1 fabric-EMIF. NOTE: The Use Debug Toolkit option will be turned on in the generated example design. 6. Save and exit the Dive Into Packaged Subsystem window. Resolution The support will begin in a future release of the Quartus® Prime Pro Edition Software.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Error (175020): The Fitter cannot place logic IO_LANE that is part of Generic Component ed_synth_phylite_s20_0_example_design, to which it is constrained, because there are no valid locations in the region for logic of this type
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.4, you may encounter a fitter issue while placing REFCLK sharing between IO48 tiles within the same banks in PHY Lite Interfaces Intel Agilex® 7 FPGA IP. Resolution These errors are due to a hardware limitation. The fitter didn't check the REFCLK location constraint because it assumes the REFCLK needs to be in the same tile.Why does the EMIF Debug Toolkit report that the Stratix® 10 DDR4 CKE*, ODT*, and RESET signals are uncalibrated?
Description The EMIF Debug Toolkit doesn't deskew the Stratix® 10 DDR4 CKE* and ODT* signals directly because the DDR4 specification doesn't include them in the address/command parity calculation. Resolution In the Address / Command Margins section, the EMIF Debug Toolkit reports all the signals that could have a delay. Still, the margins are only reported on signals that are calibrated explicitly. However, the CKE*, ODT*, and RESET signals are calibrated implicitly based on the CS* level / deskew, and therefore, their margins aren't reported. The CKE*, ODT*, and RESET signals are programmed with the same delay setting value as the CS* signals. Note that the character * refers to the memory rank number.What is the pull-up resistor guideline for the DDR4 alert_n signal?
Description The recommendation is to start with a 10k ohm pull-up resistor to 1.2V for the DDR4 alert_n signal, and then the resistor can be adjusted to a different value as long as it meets the FPGA I/O buffer VIL and VIH specifications (refer to the FPGA device datasheet under the I/O Standards specification). Perform a board signal integrity simulation to verify the optimal setting.Why did the Timing report fail in the Agilex™ 7 FPGA M-Series External Memory Interface DDR4 DIMM Design Example?
Description The following Lockstep DDR4 DIMM configurations may be unable to meet timing requirements: DDR4 DIMM x64 DDR4 DIMM x64 + ECC DDR4 DIMM x72 Resolution Please constrain the user clock to a small region, or if possible, lower the operating frequency. If these workarounds do not solve the Timing violation, please reach out to your Altera sales representative for further assistance.Can the slew rate be changed in the EMIF IP for Intel Agilex® 7 FPGA devices?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.2 and earlier, the slew rate parameter in the EMIF IP for Intel Agilex® 7 FPGA devices cannot be changed. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.Error(18090): External memory and PHYLite interfaces must share a common clock and reset signals when constrained to the same I/O column.
Description Due to a problem in the Intel® Quartus® Prime software version 19.2 or earlier, you may see the fitter error message when you aren't sharing the same clock and reset signals across multiple Intel Arria® 10 EMIF IPs in the same I/O column. This message is incorrect, and you can follow the guidelines described in the Intel® Arria® 10 EMIF IP User Guide. To place multiple interfaces in the same I/O column, you must ensure that each interface's global reset signals (global_reset_n) come from the same input pin or signal. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.Why does the Intel® Arria® 10 DDR4 IP not correct an ECC error?
Resolution A correctable bit error will not be corrected in the Intel® Arria® 10 DDR4 IP when a data mask does not correspond to a full byte (for example, a 4-bit data mask). This is because the ECC logic can only support read-modify-write on a byte-wide basis.
