Why does my EMIF IP RDIMM design have invalid assignments for SDA/SCL signals after compilation?

Description

Due to a problem in the Quartus® Prime Pro Edition software versions 25.1.1, 25.3, and 25.3.1, the Fitter does not automatically place the I2C SDA/SCL signals when they are not explicitly assigned.

Resolution

To work around the problem, manually assign legal locations for the following signals on the AC1 lane:

• SDA: index 10
• SCL: index 11

For details, see the “Address and Command Pin Placement” table in the External Memory Interfaces Agilex™ 7 M‑Series FPGA IP User Guide (DDR5): Address and Command Pin Placement.

Additional Information

Affected Quartus® Prime versions:

• 25.1.1
• 25.3
• 25.3.1

This problem is currently scheduled to be resolved in a future release of the Quartus^® Prime Pro Edition Software.