Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices.

Resolution

This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.