Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905
Description When targeting the Arria® 10 DDR4 IP and running the EMIF Toolkit in the Quartus® Prime Pro Software versions 19.2 or earlier, you may see the errors below. Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905 interface_id < EMITT_NF_EMIF_131_MAX_NUM_MEM_INTERFACES Stack Trace: 0xe3bae: EMITT_HARDWARE_READER_NF_EMIF_131::load_param_tables 0x71e (sld_emitt) 0xe1d24: EMITT_HARDWARE_READER_NF_EMIF_131::establish_connection 0x254 (sld_emitt) 0x5eb5e: emitt_establish_connection 0x31e (sld_emitt) ... End-trace Resolution To work around this problem, set the Interface ID parameter (in the Calibration Debug Options under the Diagnostics tab of the DDR4 IP) to a value equal to 10 or less. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.
Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,What is the maximum memory clock frequency for DDR4 in Arria® 10 FPGAs and SoC FPGAs?
Description In Quartus® Prime Pro Edition software version 24.3, users can configure the memory clock frequency to 1333 MHz in the External Memory Interfaces Arria® 10 FPGA IP. However, the External Memory Interfaces Arria 10 FPGA IP User Guide specifies a maximum supported configuration of 1200 MHz. Resolution Users may choose to operate the External Memory Interfaces Arria 10 FPGA IP beyond the published specifications, including overclocking, at their own risk.Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Are there timing updates for the Stratix® 10 MX ES FPGA devices?
Description This patch includes all necessary timing updates required to ensure the robust performance of the Stratix® 10 MX ES FPGA devices. Resolution Download and install the patch below to generate a programming file (.sof) in the Quartus® Prime software version 18.0.1.Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel® Stratix® 10 MX FPGA. Resolution To work around this problem, download and install the Intel® Quartus® Prime Pro Edition Software version 19.1 patch 0.04 from the appropriate link below. After installing the patch, follow the steps shown in the Readme file. Download patch Quartus-19.1-0.04-windows.exe for Windows (.exe) Download patch Quartus-19.1-0.04-linux.run for Linux (.run) Download the Readme for patch Quartus-19.1-0.04-readme.txt (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2.Why does External Memory Interface (EMIF) calibration fail on A5ED013BB23AE4/5/6SR0 devices when using Quartus® Prime Pro Edition Software version 24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might see EMIF calibration failure when targeting the following Agilex™ 5 devices. To enable the hardware support for External Memory Interfaces for the following OPNs in Quartus® Prime Pro Edition Software version 24.2, please install patch 0.09. A5ED013BB23AE4SR0 A5ED013BB23AE5SR0 A5ED013BB23AE6SR0 Resolution Download and install Patch 0.09 for the Quartus® Prime Pro Edition Software version 24.2. Then, generate the EMIF IP and compile the design after installing the patch Quartus® Prime Pro Edition Software v24.2 Patch 0.09. Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Windows (.exe) Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v24.2 Patch 0.09 (.txt)How can I enable a fixed 4x refresh rate mode for External Memory Interface IP in Intel Agilex® 7 FPGA devices?
Description Configurable fine granularity refresh mode is not supported in Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier. Resolution To enable this feature in Intel® Quartus® Prime Pro Edition Software version 21.2, download and install the following patch. Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Linux (.txt) To enable this feature in Intel® Quartus® Prime Pro Edition Software version 21.3, download and install the following patch. Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Linux (.txt) This feature is enabled by default in Intel® Quartus® Prime Pro Edition Software version 21.4 and later.Why do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently?
Description You might observe the read data corruption when there is a large difference in the calibrated DQS-en setting between calibration attempts with the Stratix® 10 FPGA QDRII+ intellectual property (IP). Resolution You can download the patch for Quartus® Prime Software v21.2 release to fix this problem. Please contact Altera support for other Quartus® Prime Software release patches. Readme for the Quartus® Prime Pro Edition Software version 21.2-0.40-readme.txt Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-windows.exe Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-linux.run