How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Are there timing updates for the Stratix® 10 MX ES FPGA devices?
Description This patch includes all necessary timing updates required to ensure the robust performance of the Stratix® 10 MX ES FPGA devices. Resolution Download and install the patch below to generate a programming file (.sof) in the Quartus® Prime software version 18.0.1.Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel® Stratix® 10 MX FPGA. Resolution To work around this problem, download and install the Intel® Quartus® Prime Pro Edition Software version 19.1 patch 0.04 from the appropriate link below. After installing the patch, follow the steps shown in the Readme file. Download patch Quartus-19.1-0.04-windows.exe for Windows (.exe) Download patch Quartus-19.1-0.04-linux.run for Linux (.run) Download the Readme for patch Quartus-19.1-0.04-readme.txt (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2.Why does External Memory Interface (EMIF) calibration fail on A5ED013BB23AE4/5/6SR0 devices when using Quartus® Prime Pro Edition Software version 24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might see EMIF calibration failure when targeting the following Agilex™ 5 devices. To enable the hardware support for External Memory Interfaces for the following OPNs in Quartus® Prime Pro Edition Software version 24.2, please install patch 0.09. A5ED013BB23AE4SR0 A5ED013BB23AE5SR0 A5ED013BB23AE6SR0 Resolution Download and install Patch 0.09 for the Quartus® Prime Pro Edition Software version 24.2. Then, generate the EMIF IP and compile the design after installing the patch Quartus® Prime Pro Edition Software v24.2 Patch 0.09. Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Windows (.exe) Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v24.2 Patch 0.09 (.txt)How can I enable a fixed 4x refresh rate mode for External Memory Interface IP in Intel Agilex® 7 FPGA devices?
Description Configurable fine granularity refresh mode is not supported in Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier. Resolution To enable this feature in Intel® Quartus® Prime Pro Edition Software version 21.2, download and install the following patch. Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.2 Patch 0.33 for Linux (.txt) To enable this feature in Intel® Quartus® Prime Pro Edition Software version 21.3, download and install the following patch. Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.13 for Linux (.txt) This feature is enabled by default in Intel® Quartus® Prime Pro Edition Software version 21.4 and later.Why do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently?
Description You might observe the read data corruption when there is a large difference in the calibrated DQS-en setting between calibration attempts with the Stratix® 10 FPGA QDRII+ intellectual property (IP). Resolution You can download the patch for Quartus® Prime Software v21.2 release to fix this problem. Please contact Altera support for other Quartus® Prime Software release patches. Readme for the Quartus® Prime Pro Edition Software version 21.2-0.40-readme.txt Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-windows.exe Patch for the Quartus® Prime Pro Edition Software version 21.2-0.40-linux.runmake: nios2-swexample-create: Command not found
Description Due to a problem in the External Memory Interfaces Intel® Stratix® 10 FPGA IP, errors may occur when compiling the Nios® II processor on-chip debug software if you enable the "Use Soft Nios Processor for On-Chip Debug" option using the Intel® Quartus® Prime Pro Edition Software v20.4 and earlier on Windows platform. make mrproper make[1]: Entering directory '/mnt/c/1/emif/ed_synth_20_4_0_72_onchipdebug_restored/ip/ed_synth/ed_synth_emif_s10_0/altera_emif_arch_nd_191/synth' Deleting software ... rm -rf software/software/emif_export_bsp rm -rf software/software/emif_export_app rm -rf software make[1]: Leaving directory '/mnt/c/1/emif/ed_synth_20_4_0_72_onchipdebug_restored/ip/ed_synth/ed_synth_emif_s10_0/altera_emif_arch_nd_191/synth' Creating hello_world_small create-this-bsp ... nios2-swexample-create \ --sopc-file=../../ed_synth_emif_s10_0.sopcinfo \ --type=hello_world_small \ --bsp-dir=software/emif_export_bsp \ --no-app make: nios2-swexample-create: Command not found Makefile:85: recipe for target 'software/emif_export_bsp/Makefile' failed make: *** [software/emif_export_bsp/Makefile] Error 127 Resolution To work around this problem, please use the Makefile instead. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.2.Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why is the I2C Avalon® Memory Mapped FPGA Host Bridge not writing to On-Chip RAM correctly when using Quartus® Prime Pro Edition Software?
Description When using the Avalon® Memory Mapped Host Bridge Core for writing into On-Chip RAM, the data might get lost or incorrectly written into memory. This behavior can be observed when writing a stream of 4 bytes to memory in certain memory offsets, in some cases, the fourth byte will not be written or misplaced into the i2c_avalon_master_address signal. This problem occurs because of the following reasons: A mishandling of an illegal byteenable condition being issued, described in the Altera® FPGA I2C Agent to Avalon Memory Mapped Host Bridge Core > Write Operation documentation. A mishandling of a multiple write burst condition or split write state performed by the Avalon Memory Mapped Host Bridge Core. This problem was found in the Quartus® Prime Pro Edition Software version 19.1 for Linux*. Resolution To overcome the problem, download the Latest Device Firmware for the Quartus® Prime Pro Edition Software version 22.2 from the following knowledge article: https://community.altera.com/kb/knowledge-base/what-is-the-latest-device-firmware-for-the-agilex%c2%ae-fpga-and-stratix%c2%ae10-fpgas/341066 This problem is fixed in the Quartus® Prime Pro Edition Software v22.3 and Quartus® Prime Standard Edition Software v22.1 onwards.
Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices. Resolution This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.