Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column
Description The following fitter error may be seen in a project implementing two independent External Memory Interfaces Cyclone®10 DDR3 IP placed in I/O banks in the same I/O column which are sharing a reset signal connected to their global_reset_n ports but not sharing clocks : Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. The following conflicting signals were found: Info(18087): Signal: <emif_0_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int Info(18087): Signal: <emif_1_path>|arch|arch_inst|non_hps.core_clks_rsts_inst|global_reset_n_int In this configuration, the DDR3 IP global_reset_n ports must be connected to the same reset signal. Note that DDR3 clock sharing (pll reference clock or core clocks) is optional. Resolution To work around this fitter error: Ensure that the Cyclone® 10 DDR3 IP parameter Diagnostics > Example Design > Enable In-System-Sources-and-Probes (ISSP) is not selected. If there is an ISSP assignment in the project .qsf file as shown below, comment it out or delete it. set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1" The enabling of ISSP in a project causes the DDR3 IP reset signals to be interpreted by the Quartus® Prime Pro Edition Software as being different, even though they are connected to the same signal source.Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905
Description When targeting the Arria® 10 DDR4 IP and running the EMIF Toolkit in the Quartus® Prime Pro Software versions 19.2 or earlier, you may see the errors below. Internal Error: Sub-system: EMITT, File: /quartus/sld/emitt/emitt_hardware_reader_nf_emif_131_impl.cpp, Line: 1905 interface_id < EMITT_NF_EMIF_131_MAX_NUM_MEM_INTERFACES Stack Trace: 0xe3bae: EMITT_HARDWARE_READER_NF_EMIF_131::load_param_tables 0x71e (sld_emitt) 0xe1d24: EMITT_HARDWARE_READER_NF_EMIF_131::establish_connection 0x254 (sld_emitt) 0x5eb5e: emitt_establish_connection 0x31e (sld_emitt) ... End-trace Resolution To work around this problem, set the Interface ID parameter (in the Calibration Debug Options under the Diagnostics tab of the DDR4 IP) to a value equal to 10 or less. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why does the Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Quartus Prime Pro Edition Software version 19.4 and later.How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller?
Description Due to a problem in the Intel® Stratix® 10 MX HBM2 controller when using the Intel Quartus® Prime Pro Edition software versions 20.4 or earlier, you may see that the AXI master returns a different value for the read address ID axi_0_0_rid signal if the read burst length axi_0_0_arlen signal is greater than 2. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 20.4 or earlier, Download hbm_burst_rid_fix.zip file and replace the following encrypted files from the existing ones. ./sim_mentor/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_191/sim/mentor/ ./syn_quartus/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_19 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.What is a possible cause of a DDR4 operational failure after upgrading to the Intel® Quartus® Prime Pro Edition software version 18.1?
Description When you select a calibrated OCT output termination setting for the Intel® Stratix® 10 DDR4 IP address/command and memory clock, it is set to a different value after upgrading from the Intel Quartus® Prime Pro Edition software version 18.0 to the Intel Quartus Prime Pro Edition software version 18.1. With the Intel Quartus Prime Pro Edition software version 18.0, the calibrated OCT output termination setting for the Intel Stratix10 DDR4 IP address/command and memory clock is set to 34 ohms, regardless of the selection made in the IP. With the Intel Quartus Prime Pro Edition software version 18.1, the calibrated OCT output termination setting for the Intel Stratix 10 DDR4 IP address/command and memory clock is set to a larger value than 34 ohms, regardless of the selection made in the IP. Resolution To work around this problem, download and install the Intel® Quartus® Prime Pro Edition software version 18.1 patch 0.20. > Download the Readme (.txt) for the version 18.1 patch 0.20 > Download the version 18.1 patch 0.20 for Windows (.exe) > Download the version 18.1 patch 0.20 for Linux (.run) With the Intel Quartus Prime Pro Edition software version 18.1 patch 0.20, select your chosen output termination with calibration setting for the Intel Stratix® 10 DDR4 IP address/command and memory clock to ensure the expected OCT analog behavior. Then regenerate the IP and recompile your design.Why do the debug toolkits print additional debug messages or stop printing messages in other cases?
Description Due to problems in the Intel® Quartus® Prime Pro Edition Software version 20.2, the debug toolkits (for example, the Intel® Stratix® 10 EMIF Unified Calibration Debug Toolkit) may print additional debug messages (including duplicate messages) which can be ignored. In other cases, the debug toolkits may print messages but then stop printing messages if the same design changes. Resolution To work around these problems in the Intel® Quartus® Prime Pro Edition Software version 20.2, download the Intel Quartus Prime Pro Edition Software version 20.2 patch 0.25. You must install the Intel Quartus Prime Pro Edition Software version 20.2, prior to installing the following patch: Version 20.2 patch 0.25 for Windows (.exe) Version 20.2 patch 0.25 for Linux (.run) Readme for the Intel Quartus Prime Pro Edition Software version 20.2 patch 0.25 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.Why does EMIF for HPS LPDDR4 fail calibration on the Agilex® 5 FPGA and SoC FPGA?
Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex® 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution This issue is fixed in 24.3.1 Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txtWhy does the EMIF or HPS EMIF calibration fail when sharing the IO Bank with the MIPI D-PHY IP？
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may observe Fabric EMIF calibration failure or HPS EMIF calibration failure when the Fabric EMIF or HPS EMIF is sharing the same IO Bank with MIPI D-PHY IP. This problem does not impact the DDR4 and DDR5 HPS EMIF implementation that is sharing only the RZQ pin with the MIPI D-PHY IP. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1,Are there timing updates for the Stratix® 10 MX ES FPGA devices?
Description This patch includes all necessary timing updates required to ensure the robust performance of the Stratix® 10 MX ES FPGA devices. Resolution Download and install the patch below to generate a programming file (.sof) in the Quartus® Prime software version 18.0.1.