How is the Intel® Stratix® 10 DDR4 IP chip select signals mapped for the top and bottom memory devices in a clamshell topology?
Description When the clamshell topology is enabled in the Intel® Stratix® 10 DDR4 IP Parameter Editor, each rank requires two CS pins to configure the top and bottom memory chips separately. The following content shows how to map the CS pins from FPGA to memory chips in single-rank and dual ranks designs. Resolution For single-rank components: The Top (non-mirrored) components, FPGA_CS0, goes to MEM_TOP_CS0 The bottom (mirrored) components, FPGA_CS1, goes to MEM_BOT_CS0 For Dual-Rank components: The Top (non-mirrored) components, FPGA_CS0 goes to MEM_TOP_CS0 and FPGA_CS1 goes to MEM_TOP_CS1 The bottom (mirrored) components, FPGA_CS2 goes to MEM_BOT_CS0 and FPGA_CS3 goes to MEM_BOT_CS1Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why do I see different Stratix® 10 Quartus® Prime Pro Edition Software generated DDR4 IBIS pin model at same bus signals ?
Description This is expected in the DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. The IBIS model is based on pin location and function in the design. In the x8/9 design, some of the DQ or Address/Command pins are located on a pin supporting DQS functionality (in x4 interfaces). The physical properties of the I/O pins that support both DQ and DQS functions are slightly different than the pins that only support DQ functions, so Quartus® Prime Pro Edition Software uses different models to improve the accuracy of the simulation. Resolution This is an example DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. You can see the mem_a(14) and mem_a(13) pins are assigned to the DQS functionality pin and have a different IBIS model name than other mem_a pins. mem_a(14)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(13)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(12)~pad sstl12_rtio_r34cp1_lv mem_a(16)~pad sstl12_rtio_r34cp1_lv mem_a(15)~pad sstl12_rtio_r34cp1_lv mem_a(2)~pad sstl12_rtio_r34cp1_lv mem_a(6)~pad sstl12_rtio_r34cp1_lv mem_a(0)~pad sstl12_rtio_r34cp1_lv mem_a(3)~pad sstl12_rtio_r34cp1_lv mem_a(7)~pad sstl12_rtio_r34cp1_lv mem_a(1)~pad sstl12_rtio_r34cp1_lvWhich I/O standards support the VCCIO_XX VREF_MODE (Internal VREF) assignment when using Stratix® 10 devices?
Description For Stratix® 10 devices, POD-12, SSTL-12, HSTL-12 Class I and Class II are I/O standards that support internal VREF. However, the internal VREF is only available for External Memory Interface (EMIF) use cases. Resolution Different applications or protocols will have different options of I/O standards available that support Internal VREF. More information about this can be found in the External Memory Interfaces Stratix® 10 FPGA IP User Guide.Why is the input parallel termination value not shown in the Intel® Quartus® Prime fitter report for Input Pins and Bidirectional Pins?
Description Starting in the Intel® Quartus® Prime Pro Edition software version 19.3, input terminations using parallel OCT are reported in the Intel Quartus Prime Fitter > Plan Stage > Input Pins or Bidir Pins as Input Termination = ON. Previous Intel Quartus Prime Pro Edition software versions reported parallel OCT with the termination value. An example is Parallel 60 Ohm with Calibration. There is no workaround required as this is only a reporting issue. The parallel termination value is correctly set in the compiled project files with the value set in the Assignment Editor or in the case of EMIF IP as defined in the generated IP .qip file. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.Why is my External Memory Interface (EMIF) IP preset file (.qprs) ignored after copying my project to a new location or using the Quartus® archiver?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you might see that your .qprs file is not taken into account when reopening the External Memory Interface (EMIF) IP after copying your project to a new location or using the Quartus® archiver. This problem is caused by using an absolute path within the External Memory Interface (EMIF) IP .ip file. Resolution To correctly read in the .qprs file, browse to the new location of the .qprs file from within the Platform Designer. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY?
Description Altera® does not recommend terminating the mem_reset_n signal. DDR3 DIMMs typically do not use any termination on the memory reset signal. Refer to the memory vendor datasheet for any memory reset termination guidelines. Resolution Related Articles Can I use a USB Blaster download cable for AES key programming? Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller Can I place bonded transceiver channels non-contiguously in Stratix® V and Arria® GZ transceiver devices?xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see this error message while simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example with the Cadence* Xcelium* simulator. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, follow the steps below: Go to <example_design_path>/sim/ed_sim/sim/xcelium/ Open xcelium_setup.sh with your preferred text editor Locate 'USER_DEFINED_ELAB_OPTIONS' line and add the '-timescale 1ps/1ps' option. After editing xcelium_setup.sh, the 'USER_DEFINED_ELAB_OPTIONS' line will look as follows: USER_DEFINED_ELAB_OPTIONS="-timescale 1ps/1ps" Execute ./xcelium_setup.sh This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.Why is there no response in AXI read data channel in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP simulation?
Description When the signals in HBM2 AXI interface are set to unknown status before and after the read command in HBM2 simulation, you might see that there is no response in HBM2 AXI read data channel. Resolution Because there is no unkown status in actual hardware behavior, the signals in AXI interface will be captured as either 0 or 1, so the unknown status in simulation are not expected. To work around this, you can set the signlas in HBM2 AXI interface in simulation to random values instead of setting them to unknown status.Why do the debug toolkits print additional debug messages or stop printing messages in other cases?
Description Due to problems in the Intel® Quartus® Prime Pro Edition Software version 20.2, the debug toolkits (for example, the Intel® Stratix® 10 EMIF Unified Calibration Debug Toolkit) may print additional debug messages (including duplicate messages) which can be ignored. In other cases, the debug toolkits may print messages but then stop printing messages if the same design changes. Resolution To work around these problems in the Intel® Quartus® Prime Pro Edition Software version 20.2, download the Intel Quartus Prime Pro Edition Software version 20.2 patch 0.25. You must install the Intel Quartus Prime Pro Edition Software version 20.2, prior to installing the following patch: Version 20.2 patch 0.25 for Windows (.exe) Version 20.2 patch 0.25 for Linux (.run) Readme for the Intel Quartus Prime Pro Edition Software version 20.2 patch 0.25 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.