Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Error(19433): Transfer between periphery and DSP or RAM (signal name) through logic cell (signal name) will make timing transfer impossible
Description You might get this error message when compiling design connecting External Memory Interfaces Intel® Stratix® 10 FPGA IP to Block RAM directly by using the Intel® Quartus® Prime Pro Edition Software. Resolution You can avoid this error by adding one or more pipeline stages between the External Memory Interfaces Intel® Stratix® 10 FPGA IP and the Block RAM.Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup)
Description When you run EMIF or PHYLite simulation with Questa* Intel® FPGA Edition, you might see the error below: # ** Error: Failure to checkout svverification license feature. # ** Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup). Resolution 1. Questa*-Intel® FPGA Edition does not support advanced verification features. Siemens EDA QuestaSim* needs to be purchased to perform advanced verification. 2. The elaboration option -nocvg can be used as a workaround to simulate EMIF or PHYLite example designs if Questa*-Intel® FPGA Edition is used as the simulation tool.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.How do I connect Intel® FPGA DDR4 PHY-Only IP with the DFI compliant Custom DDR4 Controller?
Description The DFI-compliant custom DDR4 Controller IP doesn’t have the same IO pins as Intel® FPGA DDR4 Controller IP. Please follow the solution to implement the DDR4 EMIF interface with the DFI-compliant custom DDR4 controller IP and Intel® FPGA DDR4 PHY-Only IP. Resolution The RAS/CAS/WE signals are multiplexed with address signals A[16:14] using the ACT signal per DDR4 protocol. The AFI bus provides raw access to these pins. The customer needs to use some small adaptation logic: map the AFI signals corresponding to A[16:14] to the DFI_ADDRESS signals for A[16:14] when ACT_N is low and to RAS/CAS/WE when ACT_N is high.What is the pull-up resistor guideline for the DDR4 alert_n signal?
Description The recommendation is to start with a 10k ohm pull-up resistor to 1.2V for the DDR4 alert_n signal, and then the resistor can be adjusted to a different value as long as it meets the FPGA I/O buffer VIL and VIH specifications (refer to the FPGA device datasheet under the I/O Standards specification). Perform a board signal integrity simulation to verify the optimal setting.xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see this error message while simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example with the Cadence* Xcelium* simulator. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, follow the steps below: Go to <example_design_path>/sim/ed_sim/sim/xcelium/ Open xcelium_setup.sh with your preferred text editor Locate 'USER_DEFINED_ELAB_OPTIONS' line and add the '-timescale 1ps/1ps' option. After editing xcelium_setup.sh, the 'USER_DEFINED_ELAB_OPTIONS' line will look as follows: USER_DEFINED_ELAB_OPTIONS="-timescale 1ps/1ps" Execute ./xcelium_setup.sh This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.Why there is a Data loss on Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP write response path in non-AXI backpressure mode?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 21.4 and 22.1, data loss on the write response path in non-AXI backpressure mode is expected due to the below reasons: When AXI backpressure is not enabled in Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP, write responses may be lost. The reason is that the fabric can potentially receive two write responses in a single cycle. In non-backpressure mode, there is only a cycle’s worth of read response buffering. Data loss occurs when there are two back-to-back cycles in which a pair of write responses are received. The issue is most prevalent when the fabric clock is relatively low. Even though that reduces the write command rate at the interface, if a refresh cycle causes a lot of write commands to be buffered by the Intel® Stratix® 10 MX/NX FPGA BMC devices, there will be a corresponding flood of responses once the refresh has completed. Resolution It is recommended to instantiate the same FIFO on Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP as for AXI4 compliant backpressure handling. This does have an area penalty, but each pseudo channel's FIFO requires only one MLAB (+ some ALMs for counters). This problem is currently scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software.Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the sub messages, and then rerun the Fitter.
Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 18.1, you may see the error below during the Intel® Quartus® Prime Pro Edition Software compilation process. This problem occurs because there is no pin location that has been assigned in the design. The Intel® Quartus® Prime Pro Edition Software Compiler's Fitter attempts to place the pins into a 3V I/O Bank which does not support OCT with calibration. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Resolution To work around this problem in Intel® Quartus® Prime Pro Edition Software version 18.1, manually assign the pins to any of the LVDS I/O banks which support OCT with calibration. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.1.Why does the EMIF Traffic Generator 2.0 (TG2) tool hang and/or show incorrect readdata when configured in sequential mode?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, The TG2 tool may hang or show incorrect readdata when used in sequential mode. This issue occurs because when writing a burst of data starting at an address within the last 127 address space, with a burstlength of 127, the TG2 will attempt to write data to addresses that fall outside the memory module, causing an overflow. Resolution This issue only occurs when using sequential mode. However, when using random mode or random-sequential mode, the TG2 accounts for the burstlength when generating the memory address to avoid overflow. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.
