Error(19433): Transfer between periphery and DSP or RAM (signal name) through logic cell (signal name) will make timing transfer impossible
Description You might get this error message when compiling design connecting External Memory Interfaces Intel® Stratix® 10 FPGA IP to Block RAM directly by using the Intel® Quartus® Prime Pro Edition Software. Resolution You can avoid this error by adding one or more pipeline stages between the External Memory Interfaces Intel® Stratix® 10 FPGA IP and the Block RAM.Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup)
Description When you run EMIF or PHYLite simulation with Questa* Intel® FPGA Edition, you might see the error below: # ** Error: Failure to checkout svverification license feature. # ** Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup). Resolution 1. Questa*-Intel® FPGA Edition does not support advanced verification features. Siemens EDA QuestaSim* needs to be purchased to perform advanced verification. 2. The elaboration option -nocvg can be used as a workaround to simulate EMIF or PHYLite example designs if Questa*-Intel® FPGA Edition is used as the simulation tool.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.What can cause memory test data errors to occur when using the Intel® Stratix® 10 FPGA DDR4 EMIF IP configured for 16Gb size DDR4 memory devices ?
Description 16Gb DDR4 memory device’s datasheets may show a tRFC1 (refresh to activate or refresh command period) timing parameter requirement greater than 350ns. Due to a problem in the Intel® Stratix® 10 DDR4 EMIF IP hard controller, if the DDR4 IP tRFC parameter on the Mem Timing tab is set to a value greater than 350ns, it may not operate correctly and can cause memory test data errors. There is no IP error message shown when using the EMIF IP in the Intel Quartus® Prime Pro Edition Software earlier than version 20.3. Starting from the Intel Quartus Prime Pro Edition Software version 20.3 and EMIF IP version 19.2.2, the following error message is displayed: Error: The current device family supports a maximum tRFC value of 350ns, but the current value is 550.0. Please contact Intel for support. Resolution Where the tRFC1 parameter of greater than 350ns is required, the workaround is to change the fine granularity refresh mode so that refresh requests are issued more frequently but the DDR4 IP tRFC parameter does not exceed 350ns. Check the timing parameters in the DDR4 DIMM and component datasheets. For DIMMs, refer to the tRFC1 parameter requirement in the serial presence detect (SPD) bytes 30 & 31. As an example, for a 16Gbit size memory device which has a fine granularity refresh Fixed 1x mode and tRFC1 requirement of 550ns, set the DDR4 IP refresh parameters as shown below for commercial temperature range operation : On the Memory tab : Unselect Hide advanced mode register settings Set Fine granularity refresh = Fixed 2x On the Mem Timing tab : Set tRFC = 350ns (tRFC2 in the datasheet) Set tREFI = 3.9us For higher temperature range operation, the tREFI parameter must be decreased to the value shown in the DDR4 datasheet. Regenerate the DDR4 IP and recompile the project. Note that using the fine granularity 2x refresh mode can increase the DDR4 memory power consumption, especially when using high density memory devices. You should carefully analyze your DDR4 memory power delivery and thermal design. If the workaround is successful and the memory data tests now pass, no further action is required.What is the pull-up resistor guideline for the DDR4 alert_n signal?
Description The recommendation is to start with a 10k ohm pull-up resistor to 1.2V for the DDR4 alert_n signal, and then the resistor can be adjusted to a different value as long as it meets the FPGA I/O buffer VIL and VIH specifications (refer to the FPGA device datasheet under the I/O Standards specification). Perform a board signal integrity simulation to verify the optimal setting.xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see this error message while simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example with the Cadence* Xcelium* simulator. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, follow the steps below: Go to <example_design_path>/sim/ed_sim/sim/xcelium/ Open xcelium_setup.sh with your preferred text editor Locate 'USER_DEFINED_ELAB_OPTIONS' line and add the '-timescale 1ps/1ps' option. After editing xcelium_setup.sh, the 'USER_DEFINED_ELAB_OPTIONS' line will look as follows: USER_DEFINED_ELAB_OPTIONS="-timescale 1ps/1ps" Execute ./xcelium_setup.sh This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.How do I connect Intel® FPGA DDR4 PHY-Only IP with the DFI compliant Custom DDR4 Controller?
Description The DFI-compliant custom DDR4 Controller IP doesn’t have the same IO pins as Intel® FPGA DDR4 Controller IP. Please follow the solution to implement the DDR4 EMIF interface with the DFI-compliant custom DDR4 controller IP and Intel® FPGA DDR4 PHY-Only IP. Resolution The RAS/CAS/WE signals are multiplexed with address signals A[16:14] using the ACT signal per DDR4 protocol. The AFI bus provides raw access to these pins. The customer needs to use some small adaptation logic: map the AFI signals corresponding to A[16:14] to the DFI_ADDRESS signals for A[16:14] when ACT_N is low and to RAS/CAS/WE when ACT_N is high.How do I resolve Arria 10 External Memory Interfaces DDR4 IP read capture timing violations ?
Description When a correctly parameterized Arria® 10 DDR4 interface is configured for a 1200MHz memory clock frequency in a -1 speed grade Arria 10 FPGA device, some configurations may show small Read Capture timing violations in TimeQuest Report DDR. Resolution Here are some techniques to improve Read Capture timing margins. These are applicable for any DDR4 IP configuration and not just for 1200MHz operation. 1) Read DBI : Select the DDR4 IP Memory Tab Read DBI parameter option. Ensure you also select the correct Memory CAS latency setting parameter for Read DBI from the DDR4 memory device data sheet speed bin table for your configuration and operating frequency. 2) DQS Group skew : Reduce the value of the Maximum system skew within DQS group under the DDR4 IP Board tab. The default is set to 20ps but lower skews are achievable with careful PCB layout. 3) Use a faster speed grade DDR4 memory device. 4) Periodic OCT Recalibration : Operate the DDR4 memory IP in a configuration where periodic OCT recalibration is supported. Refer to the Parameterization message window in the QSYS parameter editor and there will be a message to indicate if Periodic OCT recalibration is enabled. Not all DDR4 configurations support this feature. Note that if Periodic OCT recalibration is enabled, it prevents the user application from accessing the DDR4 memory for a short period of time when the recalibration occurs. For further information refer to the Periodic OCT Recalibration section in Chapter 2 of the EMIF Handbook Volume 3 where it shows how to calculate this delay. In the DDR4 memory presets, the default configuration causes Periodic OCT recalibration to be disabled. To enable it: Deselect the FPGA I/O tab parameter Use default I/O settings. For Address/Command and Memory Clock, change the I/O standard to SSTL-12 Class I and set the Output Mode to be a Current Strength. Perform board level simulations to optimze the signal integrity, drive strength and terminations for your interface.Error: Execution of command "{/nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Description Due to a problem in the Quartus® Prime Standard Edition Software version 19.1 Windows* version onwards, you might see this error when generating the UniPHY-based External Memory Interface IP. Resolution Install the Windows Subsystem for Linux (WSL) on Windows OS for all Quartus® Prime Standard Edition Software versions 19.1 Windows version onwards. For more details, refer to this article. There is an additional workaround requirement if you are using Quartus® Prime Standard Edition software version 19.1 on Windows. For more details, refer to this article. There is an additional workaround if you use Windows 10 version 19.03 and later. For more details, refer to this article. Related Articles How to install the Windows Subsystem for Linux (WSL) on Windows OS? FATAL: Cannot generate IP in a Windows environment! Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
