Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.SEVERE: An error occurred while running script "::emif_cal_dbg::odt_cal::run_odt_cal_callback
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.2, you may see a similar error to the one shown below when a calibration failure occurs in the Intel Stratix® 10 EMIF Unified Calibration Debug Toolkit or the Intel Agilex® 3 FPGA EMIF Debug Toolkit. SEVERE: An error occurred while running script"::emif_cal_dbg::odt_cal::run_odt_cal_callback ": ed_synth_inst: key "65542" not known in dictionary while executing "dict get $dictionary $key" (procedure "::emif_cal_dbg::util::family_expert::get_dict_elem" line 3) invoked from within "::emif_cal_dbg::util::family_expert::get_dict_elem cal_stage [expr $val]" Resolution This example error message displays an error code “65542” when a calibration failure occurs and is not reported by the EMIF Toolkit. For the Intel® Stratix® 10 EMIF Unified Calibration Debug Toolkit, below is a list of the calibration stages and associated error codes that are not reported. Calibration Stage Error Code WRITE_LEVEL_EDGE 65541 WRITE_LEVEL_CLOCK 131077 WRITE_DESKEW_DM_CENTER 65542 MARGINING_DQ 65547 MARGINING_DM 131083 For the Intel Agilex® 3 FPGA EMIF Debug Toolkit, below is a list of the calibration stages and associated error codes that are not reported. Calibration Stage Error Code WRITE_LEVEL_EDGE: 65541 WRITE_LEVEL_CLOCK: 131077 WRITE_DESKEW_DM_CENTER: 65542 READ_DESKEW_DBI_CENTER: 65540Error(19433): Transfer between periphery and DSP or RAM (signal name) through logic cell (signal name) will make timing transfer impossible
Description You might get this error message when compiling design connecting External Memory Interfaces Intel® Stratix® 10 FPGA IP to Block RAM directly by using the Intel® Quartus® Prime Pro Edition Software. Resolution You can avoid this error by adding one or more pipeline stages between the External Memory Interfaces Intel® Stratix® 10 FPGA IP and the Block RAM.Why do I see different Stratix® 10 Quartus® Prime Pro Edition Software generated DDR4 IBIS pin model at same bus signals ?
Description This is expected in the DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. The IBIS model is based on pin location and function in the design. In the x8/9 design, some of the DQ or Address/Command pins are located on a pin supporting DQS functionality (in x4 interfaces). The physical properties of the I/O pins that support both DQ and DQS functions are slightly different than the pins that only support DQ functions, so Quartus® Prime Pro Edition Software uses different models to improve the accuracy of the simulation. Resolution This is an example DDR4 IBIS model generated from Quartus® Prime Pro Edition Software. You can see the mem_a(14) and mem_a(13) pins are assigned to the DQS functionality pin and have a different IBIS model name than other mem_a pins. mem_a(14)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(13)~pad sstl12_rtio_r34cp1_dqs_lv mem_a(12)~pad sstl12_rtio_r34cp1_lv mem_a(16)~pad sstl12_rtio_r34cp1_lv mem_a(15)~pad sstl12_rtio_r34cp1_lv mem_a(2)~pad sstl12_rtio_r34cp1_lv mem_a(6)~pad sstl12_rtio_r34cp1_lv mem_a(0)~pad sstl12_rtio_r34cp1_lv mem_a(3)~pad sstl12_rtio_r34cp1_lv mem_a(7)~pad sstl12_rtio_r34cp1_lv mem_a(1)~pad sstl12_rtio_r34cp1_lvError: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup)
Description When you run EMIF or PHYLite simulation with Questa* Intel® FPGA Edition, you might see the error below: # ** Error: Failure to checkout svverification license feature. # ** Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup). Resolution 1. Questa*-Intel® FPGA Edition does not support advanced verification features. Siemens EDA QuestaSim* needs to be purchased to perform advanced verification. 2. The elaboration option -nocvg can be used as a workaround to simulate EMIF or PHYLite example designs if Questa*-Intel® FPGA Edition is used as the simulation tool.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.
Why does U-Boot initially read incorrect information from the EMIF controller Read-Only registers, but later retrieve the correct information on Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices in Quartus® Prime Pro edition software 26.1.1 and earlier?
Description Due to a synchronization issue between U-Boot and the IOSSM firmware, U-Boot may read incorrect values from EMIF controller read-only registers, such as MAILBOX_HEADER and MEM_TOTAL_CAPACITY_INTF. This occurs when U-Boot accesses these registers before the IOSSM firmware has completed their initialization. Once the IOSSM firmware initializes the registers, subsequent reads return the correct values. This issue is observed in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices when using Quartus® Prime Pro Edition Software version 26.1.1 and earlier releases. Resolution A permanent fix is planned for a future release and will include the following enhancements: The IOSSM firmware will set the MB_READY bit (bit 31) in the MAILBOX_HEADER register of the EMIF Controller to 1, indicating that the read-only registers have been fully initialized. U-Boot will poll the MB_READY bit in the MAILBOX_HEADER register and wait for it to be asserted before reading any other read-only registers in the EMIF Controller. This behavior will be enabled only when the CONFIG_IO96B_MB_READY Kconfig option is selected. To maintain compatibility with earlier IOSSM firmware versions that do not support the MB_READY bit, the CONFIG_IO96B_MB_READY option will be disabled by default.What can cause memory test data errors to occur when using the Stratix® 10 FPGA DDR4 EMIF IP configured for 16Gb size DDR4 memory devices ?
Description 16Gb DDR4 memory device’s datasheets may show a tRFC1 (refresh to activate or refresh command period) timing parameter requirement greater than 350ns. Due to a problem in the Stratix® 10 DDR4 EMIF IP hard controller, if the DDR4 IP tRFC parameter on the Mem Timing tab is set to a value greater than 350ns, it may not operate correctly and can cause memory test data errors. There is no IP error message shown when using the EMIF IP in the Quartus® Prime Pro Edition Software earlier than version 20.3. Starting from the Intel Quartus Prime Pro Edition Software version 20.3 and EMIF IP version 19.2.2, the following error message is displayed: Error: The current device family supports a maximum tRFC value of 350ns, but the current value is 550.0. Please contact Intel for support. Resolution Where the tRFC1 parameter of greater than 350ns is required, the workaround is to change the fine granularity refresh mode so that refresh requests are issued more frequently but the DDR4 IP tRFC parameter does not exceed 350ns. Check the timing parameters in the DDR4 DIMM and component datasheets. For DIMMs, refer to the tRFC1 parameter requirement in the serial presence detect (SPD) bytes 30 & 31. As an example, for a 16Gbit size memory device which has a fine granularity refresh Fixed 1x mode and tRFC1 requirement of 550ns, set the DDR4 IP refresh parameters as shown below for commercial temperature range operation : On the Memory tab : Unselect Hide advanced mode register settings Set Fine granularity refresh = Fixed 2x On the Mem Timing tab : Set tRFC = 350ns (tRFC2 in the datasheet) Set tREFI = 3.9us For higher temperature range operation, the tREFI parameter must be decreased to the value shown in the DDR4 datasheet. Regenerate the DDR4 IP and recompile the project. Note that using the fine granularity 2x refresh mode can increase the DDR4 memory power consumption, especially when using high density memory devices. You should carefully analyze your DDR4 memory power delivery and thermal design. If the workaround is successful and the memory data tests now pass, no further action is required. The problem has been fixed starting with Quartus® Prime Pro Edition software version 20.3.Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the sub messages, and then rerun the Fitter.
Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 18.1, you may see the error below during the Intel® Quartus® Prime Pro Edition Software compilation process. This problem occurs because there is no pin location that has been assigned in the design. The Intel® Quartus® Prime Pro Edition Software Compiler's Fitter attempts to place the pins into a 3V I/O Bank which does not support OCT with calibration. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Resolution To work around this problem in Intel® Quartus® Prime Pro Edition Software version 18.1, manually assign the pins to any of the LVDS I/O banks which support OCT with calibration. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.1.What is the pull-up resistor guideline for the DDR4 alert_n signal?
Description The recommendation is to start with a 10k ohm pull-up resistor to 1.2V for the DDR4 alert_n signal, and then the resistor can be adjusted to a different value as long as it meets the FPGA I/O buffer VIL and VIH specifications (refer to the FPGA device datasheet under the I/O Standards specification). Perform a board signal integrity simulation to verify the optimal setting.
