How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?

Description

You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration.

Resolution

To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time.

You can download the AMED tool below.

Follow the steps below to utilize the AMED tool:

1. Copy all the *.tcl files into the same directory.

2. Open a terminal:

   • On Windows*, open Command Prompt.

   • On Linux*, open Konsole or your preferred terminal.

3. Navigate to the directory containing the *.tcl files using the cd command.

4. Run the script by entering the command: tclsh multi_emif.tcl

 

Navigating the AMED GUI:

1. Select the number of designs to merge.
2. Browse and add each design’s directory path.
3. Set the output directory for the merged design.
4. (Optional) Check Run Analysis & Synthesis to complete this stage automatically.
5. Click Generate to start merging.

 

Additional Information

Note:
Ensure that you specify the installation paths for standalone Quartus® environments as applicable:

• For Windows* standalone installation, provide the path, for example:
  C:/altera_pro/25.1/quartus
• For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus).

This step is not required when using Network-Based Quartus® installations on Linux*.