Why is there a fitter failure when we are migrating x6 or x8 bonding design from 25.3 to 25.3.1?
Description Due to an improvement in Quartus® Prime Pro Edition software version 25.3.1, there is a change in the bonding placement for Agilex™ 5 GTS PMA/FEC Direct PHY IP. Following diagram shows the difference in the bonding placement between Agilex™ 5 GTS PMA/FEC Direct PHY IP in the Quartus Prime Pro Edition software version 25.3 and 25.3.1. Resolution For a workaround, for users that have designed their boards using the bonded port ordering in 25.3 or previous and do not want to change their physical pins or redesign, users can reassign their tx parallel data accordingly in RTL accordingly. Bank Mapping in 25.3 Current Mapping in 25.3.1 & Workaround for 25.3 x6 Bonding Bank 1C/4C CH3 tx_parallel_data [319:240] CH5 tx_parallel_data [479:400] --> Rearrange to tx_parallel_data [319:240] CH2 tx_parallel_data [239:160] CH4 tx_parallel_data [399:320] --> Rearrange to tx_parallel_data [239:160] CH1 tx_parallel_data [159:80] CH3 tx_parallel_data [319:240] --> Rearrange to tx_parallel_data [159:80] CH0 tx_parallel_data [79:0] CH2 tx_parallel_data [239:160] --> Rearrange to tx_parallel_data [79:0] Bank 1B/4B CH5 tx_parallel_data [479:400] CH1 tx_parallel_data [159:80] --> Rearrange to tx_parallel_data [479:400] CH4 tx_parallel_data [399:320] CH0 tx_parallel_data [79:0] --> Rearrange to tx_parallel_data [399:320] Mapping in 25.3 Current Mapping in 25.3.1 & Workaround for 25.3 x8 Bonding Bank 1B/4B CH3 tx_parallel_data [319:240] CH7 tx_parallel_data [639:560] --> Rearrange to tx_parallel_data [319:240] CH2 tx_parallel_data [239:160] CH6 tx_parallel_data [559:480] --> Rearrange to tx_parallel_data [239:160] CH1 tx_parallel_data [159:80] CH5 tx_parallel_data [479:400] --> Rearrange to tx_parallel_data [159:80] CH0 tx_parallel_data [79:0] CH4 tx_parallel_data [399:320] --> Rearrange to tx_parallel_data [79:0] Bank 1A/4A CH7 tx_parallel_data [639:560] CH3 tx_parallel_data [319:240] --> Rearrange to tx_parallel_data [639:560] CH6 tx_parallel_data [559:480] CH2 tx_parallel_data [239:160] --> Rearrange to tx_parallel_data [559:480] CH5 tx_parallel_data [479:400] CH1 tx_parallel_data [159:80] --> Rearrange to tx_parallel_data [479:400] CH4 tx_parallel_data [399:320] CH0 tx_parallel_data [79:0] --> Rearrange to tx_parallel_data [399:320]
Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool?
Description Due to a problem in the 24.3.1 release of the Quartus® Prime Pro Edition software, the tx_out_of_reset output port is unconnected in the GTS JESD204B IP Design Example in Dual Simplex PHY only mode. This error causes the system to be unable to release both the link reset and frame reset. As the IP is in reset, the IP simulation fails to start. Resolution To work around this problem in version 24.3.1 of the Quartus® Prime Pro Edition software, connect u_jesd_gts_ed_qsys_RX_TX|jesd_gts_ss_rx_tx|ds_group_jesd204b|tx_phy_ds_group_0_inst0_auto_jesd204_tx_out_of_reset (export output port to top level) to wire named tx_out_of_reset[0] in top level wrapper (intel_jesd204b_gts_ed_RX_TX.sv) Additionally, Altera recommends installing the patch in the Quartus® Prime Pro Edition Software version 24.3.1. After installing the patch, regenerate the GTS JESD204B IP Design Example and run the simulation. This problem is fixed in version 25.1 of the Quartus® Prime Pro Edition Software.Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.
Description You may see the following error when entering 805.664062 MHz into the GTS System PLL Clocks IP "Output frequency C0" field, to match the frequency requirement in the GTS Ethernet Hard IP when configured for 25G-1 Ethernet on Agilex TM 5 FPGA devices using the Quartus® Prime Pro software version 25.3.1 and earlier. Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz. Error: <filename>.intel_systemclk_gts_0: "Refclk frequency" (refclk_xcvr_freq_mhz_0) "156.250000" is out of range: "33.109482", "44.145976", "57.547433", "66.218964", "88.291952", "99.328446", "110.364940", "115.094866", "132.437928", "154.510916", "165.547410", "172.642299", "176.583904", "198.656892", "220.729880", "230.189732", "231.766374", "242.802868", "264.875856", "286.948844", "287.737165", "297.985338", "309.021832", "331.094820", "345.284598", "353.167808", "364.204302" This problem is caused by the truncated display of the System PLL frequency in the GTS Ethernet Hard IP. Resolution To work around this problem you can enter 805.6640625 MHz into the “Output frequency C0" field of the GTS System PLL Clocks IP. This problem may be fixed in a future version of the Quartus® Prime Pro software.Why there is Missing location assignment warnings on hps_io interfaces (SDMMC, UART, I3C) in Quartus® Prime Pro Edition Software version 25.1.1 and earlier?
Description Due to a problem in Quartus® Prime Pro Edition Software v25.1.1 and earlier. You might see the warnings messages “Missing location assignment” on some of the hps_io interfaces due to the mismatch interface name. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.3.Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why does Agilex™ 5 FPGA ES fails to boot from SDCard and eMMC devices in SDR104, HS400 and HS200 modes?
Description Due to a problem that is under investigation, the Agilex™ 5 FPGA ES (Engineering sample) devices may fail to boot from SD Card in SDR104 mode and from eMMC in HS400 and HS200 modes. The failure is observed in U-Boot and Linux*. In U-Boot, the signature of the failure can be seen from instability when loading any component from the device. In Linux, the failure signature is observed from ‘Buffer I/O Error on dev mmcblk0’ errors when accessing the device. Resolution At this time, there is no workaround for this problem, and it’s recommended to switch to the Agilex™ 5 FPGA Production device, in which this problem does not occur.Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 5 and Agilex™ 3 SoC FPGAs when using Quartus® Prime Pro Edition Software version 25.3.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1, Phase 2 configuration (FPGA fabric configuration from HPS) may fail on Agilex™ 5 and Agilex™ 3FPGA devices when Phase 1 and Phase 2 bitstreams originate from different designs or design revisions. This is caused by HPS IO hash mismatches between compilations. Resolution To work around this problem, download and install the patch below. You must recompile both the design generating the Phase 1 bitstream and the design generating the Phase 2 bitstream using the patched version of Quartus® Prime Pro Edition Software version 25.3.1. Additional Information HPS IO hash mismatches can also occur for other reasons independent of this Quartus® Prime Pro Edition Software problem. For more information about other potential causes and how to avoid them, refer to the HPS IO Hash Compatibility section in the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCsWhy does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.
