Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is the external loopback test failing for the GTS Dynamic Reconfiguration Controller IP in the GTS PMA/FEC Direct PHY example design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, you may notice that the external loopback test is not working correctly for the GTS Dynamic Reconfiguration Controller IP for the GTS PMA/FEC Direct PHY example design. This is due to incorrect settings in the hardware tcl scripts inside the “hwtest” folder. You may notice the external loopback test shows “DR Test Passed” in the system console; however, it does not change the DR profile for GTS PMA/FEC Direct PHY IP. Resolution As a workaround, modify the tcl script file as shown below: Go to “hardware_test_design/hwtest” folder: Replace the “dr_ctrl_csr_reg_map.tcl ” file inside the “hwtest/src” folder with the attached file. Replace the “dr_dphy_test.tcl” file inside the “hwtest/tests” folder with the attached file (hwtest.zip). This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why isn’t rx_ready asserted for 1G lane after dynamically reconfigured from CPRI 10G to CPRI 1.2G when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3.1, you may see rx_ready isn’t asserted at 1G CPRI when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled while Dynamic Reconfiguration(DR) process from CPRI 10G to CPRI 1.2G. This is because the firmware in the GTS Dynamic Reconfiguration Controller IP needs to be switched from Enable to Bypass mode. The software reset controller (SRC) logic was not correctly handling the state transition from Enable to Bypass mode. The state should be driven to ‘0’ when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled but this was not happening properly. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1.Why is the LPM_PIPELINE parameter in the LPM_CLSHIFT FPGA IP recognized in simulation but ignored in synthesis from Quartus® Prime Pro Edition Software 23.3 onwards?
Description Due to architectural revisions to the LPM_CLSHIFT FPGA IP starting with Quartus® Prime Pro Edition Software version 23.3, as a result of these changes, the LPM_PIPELINE parameter has been deprecated. Although these parameters remain configurable through the IP Parameter Editor, they will no longer be recognized or utilized by the software and are effectively ignored. This change has led to discrepancies between the simulation models, which continue to acknowledge the Pipeline parameters, and the implemented design, where they are ignored. Resolution As a temporary solution, it is necessary to manually instantiate the pipeline registers within your design to preserve the intended functionality for implementation while ensuring they are disabled during simulation. Below, you will find pipeline registers and instantiation templates for both Verilog and VHDL. These are conditioned by a SIMULATION user-defined parameter, providing flexibility to enable or disable the modules as required. Feel free to use these templates as a starting point for your manual implementation. Verilog Register Pipeline Template: module pipeline_registers #( parameter DATA_WIDTH = 8 // Set the default data width )( input wire clk, // Clock input input wire [DATA_WIDTH-1:0] data_in, // Data input output wire [DATA_WIDTH-1:0] data_out // Data output ); // Intermediate pipeline stage (registers) reg [DATA_WIDTH-1:0] pipeline_stage; always @(posedge clk) begin // Shift data through the pipeline pipeline_stage <= data_in; end assign data_out = pipeline_stage; endmodule Verilog Instantiation Template: // Instantiate the pipeline_registers module generate if (SIMULATION == 1'b1) begin : simulation_only // bypass the pipeline module assign data_out_signal = data_in_signal; end endgenerate generate if (SIMULATION == 1'b0) begin : synthesis_only // instantiation template for the pipeline module pipeline_registers #( .DATA_WIDTH(16) // Specify the data width for this instance ) pipeline_registers_inst ( .clk(clk), // Connect to system clock .data_in(data_in_signal), // Connect to input data signal .data_out(data_out_signal) // Connect to output data signal ); end endgenerate VHDL Register Pipeline Template: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- For using unsigned types entity pipeline_registers is generic ( DATA_WIDTH : integer := 8 -- Set the default data width ); port ( clk : in STD_LOGIC; -- Clock input data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); -- Data input data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0) -- Data output ); end entity pipeline_registers; architecture Behavioral of pipeline_registers is -- Intermediate pipeline stages (registers) signal pipeline_stage : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); begin process(clk) begin if rising_edge(clk) then -- Shift data through the pipeline pipeline_stage <= data_in; end if; end process; data_out <= pipeline_stage; end architecture Behavioral; VHDL Instantiation Template: -- Instantiate the pipeline_registers entity Simulation_only : if SIMULATION generate -- bypass the pipeline module data_out_signal <= data_in_signal; -- Connect to input and output data signals end generate; synthesis_only : if not SIMULATION generate -- instantiation template for the pipeline module pipeline_registers_inst : entity work.pipeline_registers generic map ( DATA_WIDTH => 16 -- Specify the data width for this instance ) port map ( clk => clk, -- Connect to system clock data_in => data_in_signal, -- Connect to input data signal data_out => data_out_signal -- Connect to output data signal ); end generate; Please ensure these templates' signal names and widths match your design specifications. Adjust the DATA_WIDTH parameter or generic as needed to fit the width of the data you are working on in your design. Additional InformationWhy am I seeing error for GTS CPRI PHY FPGA IP Example Design with Development kit option enabled for 24G or 12G rates in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the GTS CPRI PHY FPGA IP GUI allows users to generate a Development kit-based Example Design with 24G and 12G rates, even though the Agilex™ 5 E-Series Development kit does not support 24G and 12G data rates. The GUI should block these configurations, but it does not in the Quartus® Prime Pro Edition Software version 24.3. Resolution To avoid this error, please select only 10G or below rate while generating the GTS CPRI PHY FPGA IP Example Design with Development kit option selected. This problem is fixed in 24.3.1 release of the Quartus® Prime Pro edition software.Why does the Triple-Speed Ethernet FPGA IP for Agilex™ 5 FPGA devices, when configured with the 'Transceiver type' set to 'LVDS I/O', result in a fitter error for the Quartus® Prime Pro Edition software version 24.3.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, when compiling the design, you may see a fitter error indicating that the fitter cannot place 1 BYTE because there is no routing connectivity between the BYTE and the destination pin. This problem occurs because the IP submodule Agilex™ 5 LVDS SERDES IP requires specific pin parameter settings based on the intended pin lock. However, these settings are not currently exposed through the Triple-Speed Ethernet IP GUI for the Agilex™ 5 FPGA devices, which prevents the Quartus® Prime software from correctly routing the signals to the designated I/O pins. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.3.1. Download and install patch 1.18 from the link below. For Quartus® Prime Pro Edition software version 24.3.1 Download patch 1.18 for Windows (quartus-24.3.1-1.18-windows.exe) Download patch 1.18 for Linux (quartus-24.3.1-1.18-linux.run) Download the Readme for patch 1.18 (quartus-24.3.1-1.18-readme.txt) Please follow the User guide instructions for updating the PIN parameter settings. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why do reading/writing registers via JTAG return garbage value while performing hardware testing of the design example for the Triple-Speed Ethernet FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, a hardcoded JTAG master value in the basic.tcl file causes the TCL script to override the user-selected JTAG master value, leading to incorrect/invalid register reads and writes, which results in garbage values. Resolution To work around this problem and ensure that the correct JTAG master selected by the user is used during register read and write operations, perform the following steps: Replace the file <design_example_dir>/hardware_test_design/hwtest/agx/2xtbi_pma/basic/basic.tcl with the new basic.tcl file from the attachment. Run the hardware testing for the design example using the modified script files. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Error (24312): Intel Quartus Prime software detected that the pin placement in bank 3B_T has violated the Byte I/O Standard rule. Reassign pin location assignment according to the following user guides to comply with the restrictions.
Description The error message shown below will be seen during the fitter compilation stage when using the Quartus® Prime Pro Edition Software version 24.1 when no location assignments have been implemented in the Design Example generated from the Agilex™ 5 MIPI D-PHY FPGA IP. Error (24312): Quartus Prime software detected that the pin placement in bank 3B_T has violated the Byte I/O Standard rule. Reassign pin location assignment according to the following user guides to comply with the restrictions. Info (24313): For MIPI design, review "Using the Remaining I/O Pin from Same Byte Location" as outlined in the Agilex™ 5 FPGA MIPI D-PHY IP User Guide. Resolution To workaround this problem, provide a location assignment to at least one of the Agilex™ 5 MIPI D-PHY FPGA IP pins in the Design Example.
