Why there is Missing location assignment warnings on hps_io interfaces (SDMMC, UART, I3C) in Quartus® Prime Pro Edition Software version 25.1.1 and earlier?
Description Due to a problem in Quartus® Prime Pro Edition Software v25.1.1 and earlier. You might see the warnings messages “Missing location assignment” on some of the hps_io interfaces due to the mismatch interface name. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.3.Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why does Agilex™ 5 FPGA ES fails to boot from SDCard and eMMC devices in SDR104, HS400 and HS200 modes?
Description Due to a problem that is under investigation, the Agilex™ 5 FPGA ES (Engineering sample) devices may fail to boot from SD Card in SDR104 mode and from eMMC in HS400 and HS200 modes. The failure is observed in U-Boot and Linux*. In U-Boot, the signature of the failure can be seen from instability when loading any component from the device. In Linux, the failure signature is observed from ‘Buffer I/O Error on dev mmcblk0’ errors when accessing the device. Resolution At this time, there is no workaround for this problem, and it’s recommended to switch to the Agilex™ 5 FPGA Production device, in which this problem does not occur.Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 5 and Agilex™ 3 SoC FPGAs when using Quartus® Prime Pro Edition Software version 25.3.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1, Phase 2 configuration (FPGA fabric configuration from HPS) may fail on Agilex™ 5 and Agilex™ 3FPGA devices when Phase 1 and Phase 2 bitstreams originate from different designs or design revisions. This is caused by HPS IO hash mismatches between compilations. Resolution To work around this problem, download and install the patch below. You must recompile both the design generating the Phase 1 bitstream and the design generating the Phase 2 bitstream using the patched version of Quartus® Prime Pro Edition Software version 25.3.1. Additional Information HPS IO hash mismatches can also occur for other reasons independent of this Quartus® Prime Pro Edition Software problem. For more information about other potential causes and how to avoid them, refer to the HPS IO Hash Compatibility section in the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCsWhy does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does Nios® V/c processor fail to service interrupts when it is under CLINT-Vectored mode?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, the Nios ® V/c processor might fail to service any interrupts when it is under CLINT-Vectored mode. The affected interrupts are platform interrupts, software interrupt, and timer interrupt. The following are not affected by this issue: Nios ® V/c processor under CLINT-Direct, Nios ® V/m processor, and Nios ® V/g processor This is because the Board Support Package Editor fails to generate relevant macros in system.h to support CLINT-Vectored mode. Resolution To continue using CLINT-Vectored with Nios ® V/c processor, add the following macros in the system.h. #define ALT_CPU_INT_MODE 1 #define NIOSVSMALLCORE_INT_MODE 1 #define INTEL_NIOSV_C_0_DM_AGENT_INT_MODE 1 This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why is there a failure in the design if we are doing design migration for Agilex™ 3/Agilex™ 5 FPGA, with GTS Reset Sequencer from version 25.3 to 25.3.1?
Description Following an IP upgrade from version 25.3 to version 25.3.1 of the Quartus® Prime Pro Edition software, there is a port renaming involved for Agilex™ 3 FPGAS or Agilex™ 5 FPGA GTS Reset Sequencer IP. There are two ports that has been renamed for improvement purpose. Resolution For a workaround, you need to update the existing port name to the new ports that are available in the GTS Reset Sequencer IP. The existing ports that will require update are: i_src_rs_refclk_status_bus_out (25.3) --> i_src_rs_refclk_status_bus (25.3.1) o_src_rs_refclk_status_bus_in (25.3) --> o_src_rs_refclk_status_bus (25.3.1)Why is there a fitter failure when using reference clock from HVIO System PLL for FABRIC_USE_CASE in the Agilex™ 3/ Agilex™ 5 FPGA GTS System PLL Clocks IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, user will encounter fitter failure when they are using HVIO Reference Clock for Fabric_Use_Case. Resolution For a workaround, you need to set location assignment based on your selected devices in QSF assignment: Agilex™ 5 Family and Series Density Device Group Package Code Location Assignment A5E 013 A/B B23A/B32A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] A5E 028 A/B B23A/B23A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] 1B [SMHSSIPLLWRAP_X0_Y54_N1956] 4A [SMHSSIPLLWRAP_X121_Y7_N1956] A5E 065 A/B B23A/B32A 1A: [SMHSSIPLLWRAP_X121_Y7_N1956] 1B: [SMHSSIPLLWRAP_X0_Y54_N1956] 1C: [SMHSSIPLLWRAP_X0_Y101_N1956] 4A: [SMHSSIPLLWRAP_X185_Y7_N1956] 4B [SMHSSIPLLWRAP_X185_Y54_N1956] 4C [SMHSSIPLLWRAP_X185_Y101_N1956] A5D 064 A/B B32A 1A [SMHSSIPLLWRAP_X0_Y7_N2406] 1B [SMHSSIPLLWRAP_X0_Y15_N2406] 1C [SMHSSIPLLWRAP_X0_Y99_N2406] 1D [SMHSSIPLLWRAP_X0_Y107_N2406] 4A [SMHSSIPLLWRAP_X159_Y7_N2406] 4B [SMHSSIPLLWRAP_X159_Y15_N2406] 4C [SMHSSIPLLWRAP_X159_Y99_N2406] 4D [SMHSSIPLLWRAP_X159_Y107_N2406] This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why is there a simulation failure when we are generating and running the Agilex ™ 5 FPGA Example Design 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence or 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence?
Description Due to a problem in the generated example design for 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence and 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence in Quartus® Prime Pro Edition software version 25.3.1, user will encounter failed simulation result. Resolution For a workaround, upon successfully generated example design, you need to follow the steps accordingly to resolve this problem. Step 1: you are required to go to the generated design example folder, which is: intel_directphy_gts_0_example_design/example_design/rtl_folder Step 2: Open the file top.sv, then make the modification to the reset_sequencer module, sss1 at line 542. Update the o_pma_cu_clk[0] --> o_pma_cu_clk [1:0] Step 3: Modify the pma_cu_clk[0] in line number 787 in the same file (top.sv) shown below from: i_pma_cu_clk(pma_cu_clk[0]) --> i_pma_cu_clk(pma_cu_clk[1:0]) Step 4: Rerun the compilation and simulation. The example design will be able to pass simulation. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
