Why does the example design fail to generate when "Dual Simplex Applied on JESD204B PHY" is selected with "Enable Manual F" enabled and the F value greater than 4?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, you may observe the Dual Simplex (DS) PHY wrapper example design for GTS JESD204B IP fails to generate when the JESD204B DS Wrapper option is used with "Dual Simplex applied on JESD204B PHY" selected in the IP GUI, "Enable Manual F" is enabled, and the F value is set greater than 4. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.3.1.
CONSTRA error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb'
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the following or similar simulation error message when simulating a design targeting an Agilex® 7 FPGA M-Series device or an Agilex® 3 FPGA C-Series device: CONSTRA (ed_sim.phylite_ph2_0_example_design.phylite_ph2_0_example_design.core.arch_inst.phylite_clocking_inst.iopll_inst.tennm_ph2_iopll_encrypted_inst): error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb' This CONSTRA error occurs because the SystemVerilog Constraint Solver executable file cannot find simulation files due to missing directories from the Quartus installation path, under the directory <Quartus_version>/devices/10nm. The missing directories are part of the Agilex® 5 FPGA device support files. Resolution To work around this problem: Download the Agilex® 5 FPGA device support file, according to the Quartus® Prime Pro Edition Software version and operating system. Install the downloaded Agilex® 5 FPGA device support file. Simulate your design again using a fresh simulation directory. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why is the FPGA To HPS bridge not functional in a non-HPS EMIF hardware design in Agilex® 5 FPGA device in 25.3.1 release and earlier?
Description Due to an incorrect configuration in the mpfe_config register in the System Manager, performed by the SDM FW, the FPGA-to-HPS transactions will fail to complete on the Agilex® 5 FPGA device in a hardware design that does not instantiate the HPS EMIF IP created with Quartus® Prime 25.3.1 and before. The problem resides in the incorrect value that the SDM FW assigns to the mpfe_config[f2soc_intfcsel] bit when the HPS EMIF is not instantiated. Under this scenario, it is expected that the f2soc_intfcsel field has a value of ‘1', but this is set to '0’ instead. Resolution To workaround this problem, you can set the mpfe_config[f2soc_intfcsel] bit to '1' in the FSBL. The following snippet shows an example of how to do it in U-Boot SPL: #define MPFE_CONFIG_F2SOC_INTFCSEL_BIT 0 void board_init_f(ulong dummy) { : setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(MPFE_CONFIG_F2SOC_INTFCSEL_BIT)); do_bridge_reset(1, RSTMGR_BRGMODRST_FPGA2SOC_MASK ); : } This needs to be done before the FPGA-to-HPS (F2H) bridge is released from reset. This problem will be fixed in a future release. Note: If your non-HPS EMIF design instantiates the Altera ACE5-Lite Cache Coherency Translator (CCT) and, after applying the above workaround, you observe that read transactions in the FPGA-to-HPS (F2H) bridge succeed, but after a write transaction, the system hangs, you may require an additional fix in the ACCT IP that will be released together with the mpfe_config[f2soc_intfcsel] configuration fix. Please refer to Why does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?
What is the latest device firmware for the Agilex® FPGA and Stratix®10 FPGAs?
Description Altera® recommends using the latest version of the Quartus® Prime Pro Edition Software and the latest available device firmware. Please also see the following user guides: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution The latest device firmware available for the Quartus® Prime Pro Edition Software can be downloaded from the following links: Quartus Prime Pro Edition Software version 25.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.3? Quartus Prime Pro Edition Software version 25.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1? Quartus Prime Pro Edition Software version 24.3.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1? Quartus Prime Pro Edition Software version 24.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3? Quartus Prime Pro Edition Software version 24.2 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2? Quartus Prime Pro Edition Software version 24.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.1? Quartus Prime Pro Edition Software version 23.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.4? Quartus Prime Pro Edition Software version 23.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.3? Quartus Prime Pro Edition Software version 23.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.2? Quartus Prime Pro Edition Software version 23.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.1? Quartus Prime Pro Edition Software version 22.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.4? Quartus Prime Pro Edition Software version 22.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.3? Quartus Prime Pro Edition Software version 22.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.2? Quartus Prime Pro Edition Software version 22.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.1? Quartus Prime Pro Edition Software version 21.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.4? Quartus Prime Pro Edition Software version 21.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.3? Quartus Prime Pro Edition Software version 21.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.2? Quartus Prime Pro Edition Software version 21.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.1? Quartus Prime Pro Edition Software version 20.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 20.3?Why is there an "unrecognized device" error when using quartus_jli to configure or program a JAM file for flash devices of 2 GB or larger?
Description In any versions of Altera® Quartus® Prime Pro Edition Software, the quartus_jli command may report an “unrecognized device” error when a JAM file targets a flash device that is 2 GB or larger. This behavior is specific to JAM files used with large flash devices and does not occur with smaller flash sizes. Resolution Use the following workaround to avoid the error: Run the jtagconfig command to detect the connected JTAG hardware. After the hardware is detected, run quartus_jli to configure or program the JAM file. There is currently no plan to fix this behavior in a future Quartus® Prime release.Why are my high fanout cells not duplicated?
Description Due to an problem in the Quartus® Prime Pro Edition Software versions 24.3 and later, duplication of cells with high fanout is prevented even when duplication assignments such as DUPLICATE_REGISTER or DUPLICATE_SYNC_FANIN are defined explicitly. This behavior affects cells that have a driver in a different partition, including both signals and clocks. For example, a register in partition A that has its clock coming from the root partition will not be duplicated despite having the appropriate assignment. Resolution To work around this problem, remove the partitions or ensure that the affected cells are not driven by other cells in different partitions. If removing partitions from your design is not feasible, patches are available to work around this problem. Download and unzip the zip file that matches your Quartus® Prime Pro version and operating system from this KDB. Quartus® Prime Pro Edition Version Patch number 24.3 [0.36|^quartus-24.3-0.36.zip] 24.3.1 [1.30|^quartus-24.3.1-1.30.zip] 25.1 [0.38|^quartus-25.1-0.38.zip] 25.1.1 [1.29|^quartus-25.1.1-1.29.zip] 25.3 [0.28|^quartus-25.3-0.28.zip] 25.3.1 [1.07|^quartus-25.3.1-1.07.zip] Patches for versions 25.3 and 25.3.1 also address additional problems; refer to the README files for more information. This problem is fixed beginning with the Quartus® Prime pro Edition Software version 26.1.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_2
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the error above when using the I/O PLL Parameterizable Macro (ipm_iopll). The error only occurs when using non-integer values for the VCO Clocks and Output Clocks in the I/O PLL Parameterizable Macro. Resolution To work around this problem, use non‑integer values for the VCO Clocks and Output Clocks in the IOPLL IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the mailbox Client IP and FreeRTOS because the driver software of the IP doesn't support FreeRTOS. Resolution The driver software supports Hardware Abstraction Layer(HAL) and uCOS-II. Please select one of them when generating Nios® V BSP.Why does the F-Tile Ethernet Dynamic Reconfiguration (DR) design not work when one of the profiles has PTP enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.3, the F-Tile Ethernet designs using Dynamic Reconfiguration with PTP enabled on some of the profiles will fail to work correctly if the startup profile of the design does not have PTP enabled. Resolution To work around this problem, ensure that the startup profile of your dynamically reconfigurable Ethernet design has PTP enabled if any of the profiles have PTP enabled.Why do FPGA GPIO interrupts fail to trigger in the HPS GSRD for the Agilex® 5 FPGA E-Series Premium Dev Kit in release 25.3.1?
Description Due to a problem in the 25.3.1 GHRD 2.0 (Baseline) for Agilex® 5 FPGA E-Series Premium Development Kit, the FPGA GPIO interrupts fail to trigger when the push buttons are pressed. The error message observed during the interrupts exercising is the following: root@agilex5e:~# modprobe gpio_interrupt gpio_number=592 ubtr_type 2 modeprobe: FATAL: Modeule gpio_interrupt not found in directory /lib/modules/6.12.43-altera-xyz root@agilex5e:~# modprobe gpio_interrupt gpio_number=524 ubtr_type 3 modeprobe: FATAL: Modeule gpio_interrupt not found in directory /lib/modules/6.12.43-altera-xyz The problem has been rooted caused to the PIO interrupt mapping in the GHRD, which incorrectly uses IRQ18 instead of IRQ17. Resolution To workaround this problem, you need to change the PIO interrupt mapping in the GHRD to use IRQ17 instead of IRQ18. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.