Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is the external loopback test failing for the GTS Dynamic Reconfiguration Controller IP in the GTS PMA/FEC Direct PHY example design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, you may notice that the external loopback test is not working correctly for the GTS Dynamic Reconfiguration Controller IP for the GTS PMA/FEC Direct PHY example design. This is due to incorrect settings in the hardware tcl scripts inside the “hwtest” folder. You may notice the external loopback test shows “DR Test Passed” in the system console; however, it does not change the DR profile for GTS PMA/FEC Direct PHY IP. Resolution As a workaround, modify the tcl script file as shown below: Go to “hardware_test_design/hwtest” folder: Replace the “dr_ctrl_csr_reg_map.tcl ” file inside the “hwtest/src” folder with the attached file. Replace the “dr_dphy_test.tcl” file inside the “hwtest/tests” folder with the attached file (hwtest.zip). This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Why does the Dual Simplex Example Design in GTS JESD204C FPGA IP, with the data path clocking mode set to System PLL and JESD204C DS wrapper set to “Dual Simplex applied on JESD204C PHY,” fail to generate when the data rate exceeds 10,312.5 Mbps?
Description The Dual Simplex Example Design generation fails when the data rate exceeds 10,312.5 Mbps due to a System PLL clock constraint being violated. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, download and install patch from the appropriate link below. Download version 25.1 Patch 0.29 for Windows and Linux (.zip) Download version 25.1.1 Patch 1.17 for Windows and Linux (.zip) This problem is fixed beginning with the Quartus® Prime Pro Edition software versio 25.3.Why is there no video data stream output using the Agilex™ 5 DisplayPort FPGA IP Design Example when using the Agilex™ 5 FPGA E-series Premium Development Kit?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, the refclk pin of the Agilex™ 5-FPGA E Series Premium Development Kit has been shut down unexpectedly. Hence, no video data stream will be observed for all the DisplayPort Design Example variants. This issue affects the Linux* and Windows* versions of the Quartus® Prime Pro Edition software. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.3.1. Download and install Patch 1.02fw from the link below. Download patch 1.02fw for Windows Download patch 1.02fw for Linux The problem will be fixed in a future release of the Quartus® Pro Edition software.Why is the Mailbox Client HAL API unavailable for Agilex™ 5 FPGA devices?
Description In Quartus® Prime Pro Edition Software version 24.1, you might observe that the HAL Application Programming Interface (API) drivers of Mailbox Client IP are unavailable in the BSP for Nios® V designs targeting all Agilex™ 5 FPGA family devices. Other SDM-based devices are not affected. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 24.1, follow these steps: Start a Nios® V processor system with Mailbox Client IP in Quartus® Prime Pro Edition Software version 24.1. Generate the BSP, you might see that the Driver Name and Driver Version for the Mailbox Client IP are none. Navigate to the <BSP project folder>/drivers. Separately navigate to <Quartus Prime directory>/24.1/ip/altera/pgm/altera_s10_mailbox_client/HAL. Observe that both folder directories are the same – inc and src. Copy the contents of Quartus® Prime HAL folders into the BSP drivers folders, respectively. Navigate to <Quartus Prime directory>/24.1/ip/altera/pgm/altera_s10_mailbox_client/inc. Copy altera_s10_mailbox_client_regs.h into the BSP drivers/inc folder. Verify the content of the BSP inc folder is as below. Verify the content of the BSP src folder is as below. Modify the target_sources in BSP CMakeLists.txt. Add the C files in the PRIVATE column. drivers/src/altera_s10_mailbox_client.c drivers/src/altera_s10_mailbox_client_flash.c drivers/src/altera_s10_mailbox_client_flash_rsu.c drivers/src/altera_s10_mailbox_client_rsu.c drivers/src/librsu.c drivers/src/librsu_cb.c drivers/src/librsu_cfg.c drivers/src/librsu_ll_qspi.c drivers/src/librsu_misc.c drivers/src/rsu_client.c … Add the header files in the PUBLIC column. drivers/inc/altera_s10_mailbox_client.h drivers/inc/altera_s10_mailbox_client_flash.h drivers/inc/altera_s10_mailbox_client_flash_rsu.h drivers/inc/altera_s10_mailbox_client_regs.h drivers/inc/altera_s10_mailbox_client_rsu.h drivers/inc/librsu.h drivers/inc/librsu_cb.h drivers/inc/librsu_cfg.h drivers/inc/librsu_ll.h drivers/inc/librsu_misc.h drivers/inc/rsu_client.h … Modify the alt_sys_init.c in the following sections. Device headers. #include "altera_s10_mailbox_client.h" Allocate the device storage. ALTERA_S10_MAILBOX_CLIENT_INSTANCE ( MAILBOX_CLIENT, mailbox_client); Initialize non-interrupt controller device. ALTERA_S10_MAILBOX_CLIENT_INIT ( MAILBOX_CLIENT, mailbox_client); Proceed to compile the Software project. Additional Information This problem is fixed in Quartus® Prime Pro Edition Software version 24.3.Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?
Description Due to a silicon problem in Agilex™ 5 and Agilex™ 3 devices, the SRS16 capability register of the SDMMC controller incorrectly reports in the EDS8 bit (bit 18) that the controller does not support the eMMC 8-bit bus width mode. As a result, the U-Boot eMMC driver identifies 4-bit mode as the maximum supported width and configures the controller accordingly. This occurs even if the bus-width parameter is explicitly set to 8 in the device tree. Resolution To work around this problem, use the sdhci-caps and sdhci-caps-mask parameters in the U-Boot device tree to override the incorrectly reported values in the capability registers (SRS16 and SRS17). For this case, override bit 18 in SRS16 to indicate that an 8-bit bus width is supported. Example configuration: &mmc { status = "okay"; bus-width = <8>; sdhci-caps = <0x00000000 0x00040000>; sdhci-caps-mask = <0x00000000 0x00040000>; sd-uhs-sdr50; cap-mmc-highspeed; bootph-all; }; Verification in U-Boot: After applying the workaround, you can verify that the controller is using an 8-bit bus width by running the mmc info command: SOCFPGA_AGILEX5 # mmc info Device: mmc0@10808000 Manufacturer ID: 13 OEM: 4e Name: G1M15L Bus Speed: 52000000 Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 29.6 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 29.6 GiB WRREL Boot Capacity: 31.5 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected This workaround will be permanently implemented in the Agilex™ 5/Agilex™ 3 U-Boot device tree in a future release of the FPGA HPS Embedded Software.Why does simulation of example design using GTS Dynamic Reconfiguration Controller fail with Riviera* simulator but pass with all other simulators?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may see simulation of example designs using GTS Dynamic Reconfiguration Controller IP fails using Riviera simulator but passes with all other simulators. This is because simulation-specific behavior in the Riviera simulator causes failure. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why isn’t a programming (.sof) file generated for the GTS Ethernet Hard IP with PTP enabled example designs in Dynamically Reconfigurable mode when using the Quartus® Prime Pro Edition software versions 25.1.1 and 25.3?
Description Starting with the Quartus® Prime Pro Edition software version 25.1.1, it is mandatory to connect all the I/O ports to the correct PIN location. If any of the design I/O ports are floating and not properly connected, Quartus software will not be able to generate the programming file for the design compiled. This is mentioned in the Quartus Prime Pro Edition User Guide version 25.1.1 in 1.2. Generating Secondary Programming Files and provide the guidelines to the user on how to fix the Quartus software critical warning and successfully generate the programming file for your design. Why don’t I get a programming file when I compile with the.... A similar programming (SOF) file generation problem is observed when you generate the GTS Ethernet Hard IP with PTP-enabled example designs in Dynamically Reconfigurable. This is due to a missing pin assignment for the “i_todsync_sel” port. Resolution As a workaround, modify the “intel_eth_gts_hw.v” file as shown below: Comment out “input wire i_todsync_sel” port in the top entity Declare it as internal “wire i_todsync_sel=1'b1;” Recompile the design. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software.
