Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?

Description

Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard.

Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative.

Resolution

A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices.

• Download version 24.1 patch 0.47 for Windows and Linux below

This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard.

Please contact your local Sales representative or submit a request through the Support page for further support.

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.