Why does the RX alignment lock remain low when simulating the E-Tile Hard IP for Ethernet in 100G with RS(528,514) FEC and 100G with RS(544,514) FEC design examples using the Synopsys* VCS* / VCS* MX simulation tools?
Description When using the latest versions of the Synopsys* VCS* / VCS* MX simulator, RX alignment lock is remaining low for both the 100G with RS(528,514) FEC and the 100G with RS(544,514) FEC design examples of the E-Tile Ethernet Hard IP due to the presence of switch "-deraceclockdata" in the USER_DEFINED_ELAB_OPTIONS in the sim script file run_vcs.sh. This problem applies to E-Tile Ethernet Hard IP in both Stratix® 10 FPGA and Agilex® 7 FPGA devices and is limited to the 100G Design Examples. Resolution To workaround this problem, remove the option "-deraceclockdata" from the USER_DEFINED_ELAB_OPTIONS in the sim script file run_vcs.sh located in the testbench simulation directory <design_example_dir>/example_testbench. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.What can cause memory test data errors to occur when using the Stratix® 10 FPGA DDR4 EMIF IP configured for 16Gb size DDR4 memory devices ?
Description 16Gb DDR4 memory device’s datasheets may show a tRFC1 (refresh to activate or refresh command period) timing parameter requirement greater than 350ns. Due to a problem in the Stratix® 10 DDR4 EMIF IP hard controller, if the DDR4 IP tRFC parameter on the Mem Timing tab is set to a value greater than 350ns, it may not operate correctly and can cause memory test data errors. There is no IP error message shown when using the EMIF IP in the Quartus® Prime Pro Edition Software earlier than version 20.3. Starting from the Intel Quartus Prime Pro Edition Software version 20.3 and EMIF IP version 19.2.2, the following error message is displayed: Error: The current device family supports a maximum tRFC value of 350ns, but the current value is 550.0. Please contact Intel for support. Resolution Where the tRFC1 parameter of greater than 350ns is required, the workaround is to change the fine granularity refresh mode so that refresh requests are issued more frequently but the DDR4 IP tRFC parameter does not exceed 350ns. Check the timing parameters in the DDR4 DIMM and component datasheets. For DIMMs, refer to the tRFC1 parameter requirement in the serial presence detect (SPD) bytes 30 & 31. As an example, for a 16Gbit size memory device which has a fine granularity refresh Fixed 1x mode and tRFC1 requirement of 550ns, set the DDR4 IP refresh parameters as shown below for commercial temperature range operation : On the Memory tab : Unselect Hide advanced mode register settings Set Fine granularity refresh = Fixed 2x On the Mem Timing tab : Set tRFC = 350ns (tRFC2 in the datasheet) Set tREFI = 3.9us For higher temperature range operation, the tREFI parameter must be decreased to the value shown in the DDR4 datasheet. Regenerate the DDR4 IP and recompile the project. Note that using the fine granularity 2x refresh mode can increase the DDR4 memory power consumption, especially when using high density memory devices. You should carefully analyze your DDR4 memory power delivery and thermal design. If the workaround is successful and the memory data tests now pass, no further action is required. The problem has been fixed starting with Quartus® Prime Pro Edition software version 20.3.Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?
Description No, the Intel® Stratix® 10 timing model in the Intel® Quartus® Prime Pro Edition software version 18.0 Update 1 and 18.1 has a small miscorrelation. This is corrected in the Intel Quartus Prime Pro Edition software version 18.1 Update 1. These design scenarios may be affected: Designs that use source synchronous clocking Designs with transfers between the reference clock and the output clock for IOPLLs Designs with transfers between output clocks from different IOPLLs with different reference clocks Almost all designs will see timing delays change but most transfers will be unaffected because of either Common Clock Pessimism Removal (CCPR) or the transfer being asynchronous. Resolution All Intel Stratix 10 designs should be reanalyzed for timing in the Intel Quartus Prime Pro Edition software version 18.1 Update 1 or a patched version of 18.0 Update 1 or 18.1. Download and install Patch 1.45 for 18.0 Update 1 from the appropriate link below. Download the version 18.0 Update 1 patch 1.45 for Windows (.exe) Download the version 18.0 Update 1 patch 1.45 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.0 Update 1 patch 1.45 (.txt) Download and install Patch 0.31 for 18.1 from the appropriate link below. Download the version 18.1 patch 0.31 for Windows (.exe) Download the version 18.1 patch 0.31 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.1 patch 0.31 (.txt) For designs that are already in production: 1. Download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo Output -> lut8check.rpt, iobuf.rpt, paths.csv iobuf.rpt and paths.csv report the paths that are affected by the timing model change 2. If there are no paths identified as impacted, no action is needed. 3. If there are paths identified as impacted and using the Intel Quartus Prime Pro Edition software version 18.1 or earlier, rerun timing analysis using the patched version of the Intel Quartus Prime Pro Edition software version 18.0 Update 1 or 18.1 a. If there is not sufficient margin then recompile the design. b. If there is sufficient margin, you may choose to perform no action Steps to rerun timing analysis: 1. Download and install patch 1.45 for 18.0.1 or patch 0.31 for 18.1 2. Open the design using the patched version of the Intel Quartus Prime Pro Edition software 3. Go to Tools -> Timing Analyzer and open Timing Analyzer. 4. Run the following commands: a. create_timing_netlist -model slow -force_dat b. read_sdc c. update_timing_netlist lut8check.rpt reports the LUTs impacted by the problem described in KDB Why do I have functional errors in my Intel® Stratix® 10 design? If this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report.
Why is my IP license checked out and not released after using the Signal Tap Logic Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that an IP license is checked out and not released when using the Signal Tap Logic Analyzer. Resolution To work around this problem, use the standalone version of the Signal Tap Logic Analyzer. This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition SoftwareError: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, you might see this error when compiling your design in Design Space Explorer II. Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space (Command was: lmap panel_name [::qed_lib::rdb_util::get_report_panel_names_matching -panel_name {} -string_match {Synthesis||Logic Synthesis Stage||Partition*||*Optimization Results||Multiplier Implementations||Multiplier Implementation Report} -regexp_match {}] {::qed_lib::rdb_util::get_report_panel_str -panel_name $panel_name})} Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.21 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Error: invalid command name "else"
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see the error messages below when generating a VHDL simulation model in Platform Designer that includes the Remote Update IP. Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Resolution To work around this problem, generate Verilog Simulation Model for Remote Update IP. This problem is fixed beginning with the Quartus ® Prime Pro Edition Software version 26.1.Why does Nios® V processor system simulation fail with no print-out message and multiple “x” values along the processor’s signals?
Description This problem may be seen in the Synopsys* VCS* and VCS* MX simulators when simulating the Nios® V processor system generated from Quartus® Prime Pro Edition Software version 23.1 to 23.4, or Quartus® Prime Standard Edition Software version 23.1std This is due to the X-propagation support in the simulators. Resolution To workaround this problem, follow these steps: Switch off the X-propagation feature on the processor core, Generate testbench system from the Platform Designer. Navigate into the Synopsys* simulator directory. $ cd <Project>/sys_tb/sys_tb/sim/synopsys Append -xprop=xpropconfig into the shell script in the vcs or vcsmx folder. For example: USER_DEFINED_ELAB_OPTIONS=”-xprop=xpropconfig” Create a file named xpropconfig in the vcs or vcsmx folder (beside the shell script). Copy the following text into xpropconfig, and change the processor entity name. tree {<Nios V processor HDL entity name>} {xpropOff}; Run the simulator. This problem is currently scheduled to be resolved in Quartus® Prime Pro Edition Software version 24.1 and later.Why does my Stratix® 10 FPGA device hang when triggering FPGA reconfiguration via nCONFIG pin and Frequency Tamper Detection feature is enabled?
Description In Quartus® Prime Pro Edition Software version 25.1 and earlier, an issue occurs when the physical anti‑tamper feature is enabled using the Frequency Tamper Detection method in combination with an Active Serial configuration scheme. If you initiate a device reconfiguration by pulsing the nCONFIG pin, the Stratix® 10 FPGA may hang and fail to proceed with the reconfiguration process. Resolution You can recover the device by performing a power cycle. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why do I get the error Internal Error "No Active Family" when trying to generate a programming JAM file via command line "quartus_pfg"
Description When trying to generate a JAM programing file (.jam) via the quartus_pfg command line from a Chain Description File (.cdf). quartus_pfg -c <file>.cdf <file>.jam You may get the following error message: Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_jam.cpp, Line: 2873 No Active Family Stack Trace: Quartus 0x3cce3e: PGMIO_JAM::jam2_filter(int, PGMIO_JTAG_UNI_ENGINE*, std::basic_ifstream >&, std::ostream&) + 0x582 (pgm_pgmio) Quartus 0x3d0a7a: PGMIO_JAM::jam2_create_file(int, PGMIO_JTAG_UNI_ENGINE*) + 0x846 (pgm_pgmio) Quartus 0x3d4ec2: PGMIO_JAM::create_output_file(std::vector >*, FIO_PATH const&, bool) + 0x3e8c (pgm_pgmio) This error may be due to an issue were the source programming files on the .cdf file not being valid. Resolution To work around this problem, verify your programing source file or files with the following command line: quartus_pfg -i <source>.sof This command will help you determine if your source file or files are valid and invalid and provide additional info on the issues with the invalid files for troubleshooting. Replace the invalid files with valid ones once identified. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.
