Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346Why MAX® 10 FPGA programming failed when I used .jbc file with altera-stapl/JAM-STAPL player?
Description MAX® 10 FPGA programming with .jbc using altera-stapl/JAM-STAPL player failed with error log “No SLD hub”,”No SLD Node”, “Unrecognized device” and “Exit code = 6”. However, programming through Quartus® using same JBC or POF is successful. Reading ID_CODE and USER_CODE are working. Resolution Open the Quartus project’s programming or configuration-file generation settings. Enable “Enable real-time ISP to allow background programming” option. Regenerate the JAM file. Generate a new JBC from the newly created JAM file. Retry programming the MAX® 10 FPGA from the SoM using the new JBC.Why do I get "Fatal Error: Access Violation at" when running quartus_syn or quartus_fit?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 26.1 and earlier, and Quartus Prime Standard Edition Software versions 25.1 and earlier, compilation may terminate with a "Fatal Error: Access Violation" message during synthesis or fitting. This failure can occur intermittently, and the reported memory address may change between compilation runs. You may observe one or more of the following behaviors: Quartus® compilation fails during synthesis or fitting The failure may occur in either of the following modules: quartus_syn (during synthesis) quartus_fit (during fitting) The error message is similar to: *** Fatal Error: Access Violation at <<ADDRESS>> The reported memory address may change between runs. The fatal error is followed by a stack trace that includes one of the failure signatures listed below. CDB_SGATE_OTERM::adopt_fanouts HDB_ASGN_CONTAINER::remove_assignment LUTIL_DEVICE::get_fragment_from_subloc STA_NODE::reset_tag_heads DESIGN_HDB_ASSIGNMENT_CONVERTER::cleanup_after_conversion BSYN_RTM_FLOP::IsExpired RTM_ATOM_MGR::rip_out_simple_ff_for_bypass IRTM_FF_QUEUE::remove_ff PTI_BCM_TIMING_GRAPH::push_back_carry_hipi_clock_iterm FTM_TREE_NODE::num_sgates Stack traces may differ, even when compiling the same design. Specific Failure Signatures: Synthesis failure (quartus_syn): The crash report includes the following function call: RTL_ADDER::aggressive_adder_balancing Fitter failure (quartus_fit): The error occurs very early after the fitter starts, and the crash report includes the following function call: qhd_reread_global_assign_from_qsf Error Log Examples Stack Trace example for crashes in quartus_syn *** Fatal Error: Access Violation at 00007FFB92E2C63E Module: quartus_syn.exe Stack Trace: Quartus 0xc63d: CDB_SGATE_OTERM::adopt_fanouts + 0x2d (db_cdb_sgate) Quartus 0x117e7: RTL_ADDER::shrink_iports + 0x1f7 (SYNTH_OPT) Quartus 0x14a75: RTL_ADDER::create_binary_adder + 0x49e9 (SYNTH_OPT) Quartus 0x45910: RTL_ADDER::restrict_adder_network + 0x84a (SYNTH_OPT) Quartus 0x4f5d6: RTL_ADDER::aggressive_adder_balancing + 0x9d (SYNTH_OPT) Quartus 0x11533: RTL_SCRIPT::call_common_rtl_fns + 0x1043 (SYNTH_OPT) Quartus 0x115b5: RTL_SCRIPT::call_named_function + 0x8a2 (SYNTH_OPT) Quartus 0x3a87a: RTL_SCRIPT::process_script + 0x62c (SYNTH_OPT) Quartus 0x3a8e4: run_parallel_rtl + 0x1db4 (SYNTH_OPT) Quartus 0x8509d: SYNTH_QIS::SYNTHESIS_FLOW::run_parallel_rtl_in_helper_processes + 0x285 (synth_qis) Quartus 0x850d5: SYNTH_QIS::SYNTHESIS_FLOW::high_level_synthesis + 0x47d (synth_qis) Quartus 0x8546d: SYNTH_QIS::SYNTHESIS_FLOW::run_current_phase + 0x286 (synth_qis) Quartus 0x854d4: SYNTH_QIS::SYNTHESIS_FLOW::run_full_flow + 0x30d (synth_qis) Quartus 0x859b7: QIS_RTL_STAGE_IMPL::synthesize + 0x467 (synth_qis) Quartus 0x15b55: qis_synthesize + 0x245 (synth_qis) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x16f4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6ab8: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x15246: qexe_evaluate_tcl_script + 0x4e6 (comp_qexe) Quartus 0x1143b: qexe_do_tcl + 0x46b (comp_qexe) Quartus 0x1a70e: qexe_run_tcl_option + 0x5ee (comp_qexe) Quartus 0x16451: QCU::DETAIL::initialize_qhd_and_run_qexe + 0xa1 (comp_qcu) Quartus 0x1f8e2: qcu_run_tcl_option + 0x2f2 (comp_qcu) Quartus 0x1b1ba: qexe_standard main + 0x26a (comp_qexe) Quartus 0x29eb: qexe_run + 0x3eb (comp_qexe) Quartus 0x1192p: qsyn2_main + 0x1a9p (quartus_syn) Quartus 0x1e808: msg_main_thread + 0x18 (CCL_MSG) Quartus 0x17021: msg_thread_wrapper + 0x71 (CCL_MSG) Quartus 0x1c89d: mem_thread_wrapper + 0x70 (CCL_MEM) Quartus 0x1b49d: msg_exe_main + 0x20d (CCL_MSG) Quartus 0x2b6c: __scrt_common_main_seh + 0x11c (quartus_syn) Quartus 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) Quartus 0x5b3b: RtlUserThreadStart + 0x2b (ntdll) End-trace Stack Trace example for crashes in quartus_fit *** Fatal Error: Access Violation at 00007FFB8F79CFF7 Module: quartus_fit.exe Stack Trace: Quartus 0x1cff6: HDB_ASGN_CONTAINER::remove_assignment + 0x52 (DB_HDB) Quartus 0x1cf71: HDB_ASGN_CONTAINER::destroy_assignment + 0x31 (DB_HDB) Quartus 0xca69c: anonymous namespace::delete_all_global_assignments + 0x25c (comp_qhd) Quartus 0xcc344: qhd_reread_global_assign_from_qsf + 0x384 (comp_qhd) Quartus 0x51679: QHD_DATABASE_UTILS::load_design + 0x449 (comp_qhd) Quartus 0x1e1e0: FIT2_DATABASE_EXPERT_QDB::load + 0x5b0 (comp_fit2) Quartus 0x3xee: fit2_create_fitter_netlist + 0x3xee (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x16f4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6ab8: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x15246: qexe_evaluate_tcl_script + 0x4e6 (comp_qexe) Quartus 0x1143b: qexe_do_tcl + 0x46b (comp_qexe) Quartus 0x1a70e: qexe_run_tcl_option + 0x5ee (comp_qexe) Quartus 0x16451: QCU::DETAIL::initialize_qhd_and_run_qexe + 0xa1 (comp_qcu) Quartus 0x1f8e2: qcu_run_tcl_option + 0x2f2 (comp_qcu) Quartus 0x29eb: qexe_run + 0x3eb (comp_qexe) Quartus 0x16f2d: qfit2_main + 0x82d (quartus_fit) Quartus 0x1e808: msg_main_thread + 0x18 (CCL_MSG) Quartus 0x17021: msg_thread_wrapper + 0x71 (CCL_MSG) Quartus 0x1c89d: mem_thread_wrapper + 0x70 (CCL_MEM) Quartus 0x1b49d: msg_exe_main + 0x20d (CCL_MSG) Quartus 0x2b6c: __scrt_common_main_seh + 0x11c (quartus_fit) Quartus 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) Quartus 0x5b3b: RtlUserThreadStart + 0x2b (ntdll) End-trace Resolution This problem is currently scheduled to be resolved in a future release of the Quartus Prime Pro Edition Software and the Quartus Prime Standard Edition Software. If you are using Quartus Prime Pro Edition Software version 26.1, apply the attached patch for your operating system: Download the Linux or Windows patch package for your platform. On Linux, install the patch package from the console. On Windows, run the patch executable file. Confirm the installation by opening the Quartus Prime GUI and checking the About window, or by running: quartus_sh -v If applying the patch is not possible, or if you need assistance with other Quartus Prime software versions, contact your local Altera support representative. Additional Information Affected software: Quartus Prime Pro Edition Software version 26.1 and earlier Quartus Prime Standard Edition Software version 25.1 and earlierWhat is the GPIO pin state after full power-up and before configuration mode for MAX® 10 FPGA devices?
Description For MAX® 10 FPGA devices, GPIO pins are typically tri-stated with weak pull-up enabled after full power-up and before configuration mode, except for the pin identified in the table below for each device package. That pin is tri-stated without weak pull-up enabled during this period, but it functions correctly in user mode. Device Package Type Y180 180-pin WLCSP M153 153-pin MBGA U169 169-pin UBGA U324 324-pin UBGA B610 610-pin VPBGA E144 144-pin EQFP 10M02 — D7 E6 C5 — 128 10M04 — D7 E6 C5 — 132 10M08 — D7 E6 C5 — 132 10M16 A5 — E6 C5 — 132 10M25 — — — — — 132 10M40 — — — — P18 133 10M50 — — — — P18 133 Device Package Type U324 324-pin UBGA F256 256-pin FBGA B610 610-pin VPBGA F484 484-pin FBGA F672 672-pin FBGA 10M02 C5 — — — — 10M04 C5 B5 — — — 10M08 C5 B5 — E8 — 10M16 C5 B5 — E8 — 10M25 — B5 — E8 — 10M40 — B5 P18 E8 E10 10M50 — B5 P18 E8 E10 Resolution This is expected behavior. If your system depends on the GPIO pin state during this period, consider adding an external pull-up resistor to the pin or selecting a different GPIO pin in your design.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for Simulation
Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex® 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows* and Linux* below This patch ensures the transmitter maintains negative running disparity for Agilex® 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1.
