Why does the Intel® Quartus® Prime Standard Edition software fail to choose the 1.0V IO standard for Intel® MAX® 10 devices?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition software version 20.1 and earlier, you may not be able to choose the 1.0V IO standard for 10M02/04/08/16 SAU324C8G Intel® MAX® 10 devices. Resolution To work around this problem, download and install the Intel® Quartus® Prime Standard Edition software version 20.1 patch 0.11 from the appropriate link below. After installing the patch, follow the steps provided in the readme files. Download patch quartus-20.1std-0.11std-windows.exe for Windows (.exe) Download patch quartus-20.1std-0.11std-linux.run for Linux (.run) Download the Readme for patch quartus-20.1std-0.11std-readme.txt (.txt)When does the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?Can I perform multiple compilations at the same time on one computer with a single-seat license?
Description You cannot perform multiple simultaneous compilations using the Quartus® Prime Software if you have a floating license with a single license seat. The number of concurrent compilations that can be run on a single computer cannot exceed the number of available license seats. If you have one fixed (node-locked) license, you can run multiple simultaneous compilations on that machine. Resolution See the related solution below for details on when the Quartus® Prime Software checks for available licenses. Related Articles When is a license checked out by the Quartus II software, IP cores and ModelSim-Altera Edition software?Why does Nios® V processor system simulation fail with no print-out message and multiple “x” values along the processor’s signals?
Description This problem may be seen in the Synopsys* VCS* and VCS* MX simulators when simulating the Nios® V processor system generated from Quartus® Prime Pro Edition Software version 23.1 to 23.4, or Quartus® Prime Standard Edition Software version 23.1std This is due to the X-propagation support in the simulators. Resolution To workaround this problem, follow these steps: Switch off the X-propagation feature on the processor core, Generate testbench system from the Platform Designer. Navigate into the Synopsys* simulator directory. $ cd <Project>/sys_tb/sys_tb/sim/synopsys Append -xprop=xpropconfig into the shell script in the vcs or vcsmx folder. For example: USER_DEFINED_ELAB_OPTIONS=”-xprop=xpropconfig” Create a file named xpropconfig in the vcs or vcsmx folder (beside the shell script). Copy the following text into xpropconfig, and change the processor entity name. tree {<Nios V processor HDL entity name>} {xpropOff}; Run the simulator. This problem is currently scheduled to be resolved in Quartus® Prime Pro Edition Software version 24.1 and later.Why does the HDMI Design Example fail to generate when using the Quartus® Prime Standard Edition Software version 24.1?
Description From Quartus® Prime Standard Edition Software version 24.1 onwards, Nios® II has been removed and is now End-of-Life (EOL). The HDMI Design Example hasn't been upgraded to Nios® V yet, and so this causes the design example generation to fail. The error below will be seen when trying to generate the design example for the listed device families: "Error: Failed to generate example design example_design to: " Resolution No workaround for this problem exists. If necessary, use the Quartus® Prime Standard Edition Software version 23.1 until this problem is resolved in a future release. Additional Information This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why are the 'Host ID Type' and 'Host ID Value' shown as 'Not Found' when setting up a floating license in the Quartus® Prime Standard Edition Software?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1, the Host ID Type and Host ID Value might be shown as Not Found when setting up a floating license file in the Quartus® Prime Software. This is a GUI problem; the license will still be properly checked during compilation. To determine whether the license file is loaded, check that the license information is displayed in the Licensed AMPP/Megacore functions dialog box. This problem does not occur when setting up a fixed license file. Resolution This problem is fixed beginning with the Quartus ® Prime Standard Edition Software version 25.1. This problem does not occur in the Quartus® Prime Pro Edition Software.
Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex® 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows* and Linux* below This patch ensures the transmitter maintains negative running disparity for Agilex® 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1.What should I consider when designing a system board using Schmitt trigger inputs on MAX® 10 FPGAs?
Description When designing a system board that uses Schmitt trigger inputs on MAX® 10 FPGAs, board-level noise, power integrity, and signal integrity can significantly affect the effective hysteresis behavior. Factors such as power supply noise, input signal noise, and PCB layout practices may cause the observed switching thresholds to deviate from their typical values. This article outlines key considerations to help minimize noise sensitivity when using Schmitt trigger inputs in a system-level design Resolution When designing a system board that uses Schmitt trigger inputs, consider the following: Follow the recommendations in the MAX® 10 FPGA Design Guidelines, especially sections related to power distribution network (PDN) and signal integrity. Minimize power supply noise by using proper decoupling, grounding, and PCB layout practices. Note: The MAX® 10 FPGA 10M08 Evaluation Kit is intended for low-cost application testing and is not designed for DC or PDN characterization. It should not be used to measure intrinsic transistor switching thresholds.Why does the Nios® V processor force Configuration Scheme with Memory Initialization for MAX® 10 FPGA?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and 24.1, you may see an error below when using Dual Compressed Image as the Internal Configuration mode for Nios® V Processor Design on MAX® 10 FPGA, Error (16031): The current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. Note: Assuming that memory initialization is disabled in every on-chip memory. Resolution To work around this problem, Download and install the patches below for the Quartus® Prime Standard Edition Software version 24.1. Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Windows (.exe) Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std (.txt) Download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1. Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Windows (.exe) Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std (.txt) The problem has been fixed starting with Quartus® Prime Standard Edition software version 25.1,