Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?

Description

In the Quartus^® Prime Standard Edition software version 25.1, any Nios^® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus^® Prime project.   

Here are the possible error messages that you might receive: 

• Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'";  expecting ":", or "?", or binary operator. 

• Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) 

• Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions 

• Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead 

• Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored 

 

This is because the Quartus^® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below.

 

This requirement is not mandatory in prior versions of the Quartus^® Prime Standard Edition software. 

Resolution

To work around this problem in the Quartus^® Prime Standard Edition Software version 25.1, 

1. Remove the QSYS file from the project using the Remove Files in Project function. 

1. Add the QIP file to the project using the Add Files in Project function. 

 

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