Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.How do I use the CHANGE_EDREG instruction to simulate a CRC error in Intel® Cyclone® 10 LP device?
Description You can perform CHANGE_EDREG using quartus_jli command with an appropriate JAM STAPL Format File (.jam) file in Intel® Cyclone® 10 LP device. You can download an example crc-edreg-c.jam. Here are the steps to execute quartus_jli command with the example .jam file Connect your PC to your Intel Cyclone 10 LP device through a download cable Configure your Intel Cyclone 10 LP device Open a command prompt when using Windows or a command shell when using Linux Execute the following command quartus_jli -c <cable number> -a CONFIG_IO crc-edreg-c.jam The cable number can be identified by using jtagconfig command. After CHANGE_EDREG is executed successfully, the 32-bit storage register of the error detection block is modified and a CRC error is detected.Error (292019): IP core 6AF7_0014 not supported in device family Cyclone 10 LP
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 17.1, you may see this errror when you compile NCO IP with a valid NCO IP license. Resolution A patch is available to fix this problem for the Quartus Prime Standard Edition software version 17.1. Download and install Patch 0.07std from the appropriate link below Download the Quartus Prime Standard Edition software version 17.1 Patch 0.07 for Windows (.exe) Download the Quartus Prime Standard Edition software version 17.1 Patch 0.07 for Linux (.run) Download the Readme for the Quartus Prime Standard Edition software version 17.1 Patch 0.07 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 18.0.Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n). This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File (.qsf): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Is there a known issue with simulating the Cyclone® 10 FPGA LP PLL IP using Verilog?
Description Due to a problem in the Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 FPGA LP devices when performing Verilog simulation. This issue does not apply when simulating the Cyclone® 10 FPGA LP PLL IP using VHDL. Resolution To fix this issue, install the patch below on top of Quartus® Prime Standard version 17.0 and follow the instructions to add extra steps in your simulation run script. if ![file isdirectory verilog_libs] { file mkdir verilog_libs } vlib verilog_libs/altera_mf_ver vmap altera_mf_ver ./verilog_libs/altera_mf_ver vlog -vlog01compat -work altera_mf_ver {c:/intelfpga/17.0/quartus/eda/sim_lib/altera_mf.v} This problem is fixed beginning with the Quartus® Prime Standard Edition software version 18.0.Why do Cypress* flash devices S25FL256 and S25FL512 not get programmed with Intel® Quartus® Prime Standard Edition Software version 18.1 when using Intel® Cyclone® 10 LP or legacy devices?
Description Due to a problem in the Intel® Quartus® Programmer Standard Edition software version 18.1, Cypress* flash devices with a density of 256 MB and 512 MB will fail to get programmed correctly. The Intel® Quartus® programmer may show successful programming, but the Flash would not actually be programmed. Resolution To work around this problem, download and install patch 0.05 from the links below. You must install the Intel® Quartus® Prime Standard Edition Software version 18.1 before installing this patch. Download the version 18.1std patch 0.05std for Windows (.exe) Download the version 18.1std patch 0.05std for Linux (.run) Download the Readme for the Intel Quartus Prime Standard software version 18.1 patch 0.05std (.txt) This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 19.1.Are there any functional or security updates for the Quartus® Prime Standard Edition Software version 23.1.1?
Description The Quartus® Prime Standard Edition Software version 23.1.1 Patch 1.01std includes functional and security updates. Users should keep their software up-to-date and follow the technical recommendations to help improve security. If you need additional security updates, they will be provided in this article as they become available. Resolution A patch is available to include this update for the Quartus® Prime Standard Edition Software version 23.1.1 and the Quartus® Prime Lite Edition Software Version 23.1.1. Download and install Patch 1.01std below. This problem has been fixed starting with the Quartus® Prime Standard Edition Software version 25.1 and the Quartus® Prime Lite Edition Software version 25.1.Why does the Quartus® Prime Standard Edition Software version 22.1 downwards show "Error (165012): The DQS pin 'dpclk' has a dual-purpose clock pin delay setting, but it is constrained to a pin at location 'PIN XX' that does not support this setting"?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 downwards, an error is shown when adding the dual-purpose clock input pin delay to the DPCLK pin of the Cyclone® 10 LP FPGA. Resolution There is no workaround currently, and there is no plan to fix this problem.Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.
