Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.
Why does Nios® V processor system simulation fail with no print-out message and multiple “x” values along the processor’s signals?
Description This problem may be seen in the Synopsys* VCS* and VCS* MX simulators when simulating the Nios® V processor system generated from Quartus® Prime Pro Edition Software version 23.1 to 23.4, or Quartus® Prime Standard Edition Software version 23.1std This is due to the X-propagation support in the simulators. Resolution To workaround this problem, follow these steps: Switch off the X-propagation feature on the processor core, Generate testbench system from the Platform Designer. Navigate into the Synopsys* simulator directory. $ cd <Project>/sys_tb/sys_tb/sim/synopsys Append -xprop=xpropconfig into the shell script in the vcs or vcsmx folder. For example: USER_DEFINED_ELAB_OPTIONS=”-xprop=xpropconfig” Create a file named xpropconfig in the vcs or vcsmx folder (beside the shell script). Copy the following text into xpropconfig, and change the processor entity name. tree {<Nios V processor HDL entity name>} {xpropOff}; Run the simulator. This problem is currently scheduled to be resolved in Quartus® Prime Pro Edition Software version 24.1 and later.Why does the HDMI Design Example fail to generate when using the Quartus® Prime Standard Edition Software version 24.1?
Description From Quartus® Prime Standard Edition Software version 24.1 onwards, Nios® II has been removed and is now End-of-Life (EOL). The HDMI Design Example hasn't been upgraded to Nios® V yet, and so this causes the design example generation to fail. The error below will be seen when trying to generate the design example for the listed device families: "Error: Failed to generate example design example_design to: " Resolution No workaround for this problem exists. If necessary, use the Quartus® Prime Standard Edition Software version 23.1 until this problem is resolved in a future release. Additional Information This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why are the 'Host ID Type' and 'Host ID Value' shown as 'Not Found' when setting up a floating license in the Quartus® Prime Standard Edition Software?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1, the Host ID Type and Host ID Value might be shown as Not Found when setting up a floating license file in the Quartus® Prime Software. This is a GUI problem; the license will still be properly checked during compilation. To determine whether the license file is loaded, check that the license information is displayed in the Licensed AMPP/Megacore functions dialog box. This problem does not occur when setting up a fixed license file. Resolution This problem is fixed beginning with the Quartus ® Prime Standard Edition Software version 25.1. This problem does not occur in the Quartus® Prime Pro Edition Software.Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Is there any problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices?
Description No, there is no problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices. Leakage can occur between VCC and VCCIO as well as between VCC and VCCPT, which can cause both VCCIO and VCCPT to float up to a maximum approximation of 0.8V before the power supply is ramped up and after the power supply is ramped down. This is expected behavior, and if the power-up and power-down sequences are followed, it will neither cause any functional failure nor concern the device's reliability. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down. Resolution This is an expected behavior and will neither cause any functional failure nor reliability concern to the device if the power-up sequence and power-down sequence are followed. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down.Why does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why are some simulation library files missing when compiling for Questasim*?
Description Due to a problem in Simulation Library Compiler in the Quartus® Prime Standard Edition Software 23.1 and later, you may see some Quartus® Simulation Library source files not included for compilation for Siemens* Questasim* Tool selection. This problem persists on both EDA Simulation Library Compiler GUI and command line versions. This problem only exists in Quartus® Prime Standard Edition and does not affect Quartus® Prime Pro Edition versions. Resolution To work around this problem, follow these steps: 1. Edit file: <QUARTUS INSTALLATION DIRECTORY>/quartus/common/tcl/internal/simlib_comp.tcl 2. Replace: set gl(primary_tool,questasim) questasim With: set gl(primary_tool,questasim) modelsim This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the outclk of the ALTCLKCTRL IP remain enabled when using the ENA input in External Path mode?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 or earlier, you might see that the output clock of the ALTCLKCTRL IP remains enabled regardless of whether the ENA input is asserted or de‑asserted when using the “External path” mode. This problem occurs because the ENA input port is not used in “External path” mode even if the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option is selected. Beginning with the Quartus® Prime Standard Edition Software version 23.1, the software will generate an error message indicating that the “Create ‘ena’ port” option is unavailable when the “External path” type is selected. Resolution To work around this problem using the ALTCLKCTRL IP with the “External path” mode: Disable the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option in the Parameter Editor. If you require clock gating, implement the gating logic external to ALTCLKCTRL (for example, gate the source clock or use an alternate supported clock‑control scheme) rather than relying on the ALTCLKCTRL ENA port in “External path” mode.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387
