Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?

Description

Due to a problem in the Quartus^® Prime Standard Edition software version 25.1, Nios^® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design.

This problem affects:

All Altera^® FPGA device families in Quartus^® Prime Standard Edition software, and

All Nios^® V processor variants (Nios^® V/g, Nios^® V/m, and Nios^® V/c processors).

It is because the generation of the Nios^® V processor VHDL testbench system is not supported in Quartus^® Prime Standard Edition software version 25.1.

Resolution

To work around this problem in the Quartus^® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. 

This problem is currently scheduled to be resolved in a future release of the Quartus^®Prime Standard Edition software.

3.3.1. Preparing Hardware Design for Simulation

Published 14 days ago

Version 1.0

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