Why USB-Blaster II does not work after closing the Quartus® Programmer Hardware Setup window?
Description When using Quartus® Prime Standard Edition to program a MAX® 10 FPGA device with a USB-Blaster II, changing the Hardware Setup frequency from the default 24 MHz to 16 MHz and then closing the Hardware Setup window with the Close button may cause the USB-Blaster II to stop functioning. Resolution Here are some practical solutions you can try to resolve the issue: 1. Restart the JTAG server. jtagserver --stop jtagserver --start 2. Unplug and replug the USB-Blaster II. 3. Kill lingering processes such as the JTAG server or Quartus Programmer process. jtagserver.exe quartus_pgm.exe 4. Change the clock frequency of the USB-Blaster II download cable to lower frequency like 16Mz and 6Mz. Related KDB: How do I change the clock frequency of the USB-Blaster II download cable? | Altera Community - 342304 5. Avoid USB conflicts by disconnecting other USB serial devices, especially FTDI or USB-UART adapters, and avoid opening COM ports or serial terminal applications while programming. 6. Try a different USB port and connect the USB-Blaster II directly to the PC instead of through a USB hub. 7. Reinstall the driver from the Quartus installation folder or try an older or known-stable driver version. 8. Avoid mixing drivers from multiple Quartus versions. 9. If a USB hub is required, avoid poor-quality or legacy USB 1.0 hubs. 10. If a clone USB-Blaster is being used, replace it with a known-good cable. 11. If none of the above steps recover the problem, reboot the system. Possible root causes: 1. JTAG server gets stuck and keeps the USB-Blaster II claimed. The device can appear normal in the operating system but remain inaccessible from Quartus Programmer. Restarting Quartus alone often does not recover the cable. Fix: jtagserver --stop jtagserver --start Or kill the process via Task Manager. 2. USB or driver conflicts with other devices. Conflicts with other devices, especially FTDI or USB-UART adapters, can break the USB-Blaster II mid-session. Opening a serial terminal can trigger the failure. This behavior is reported more often on Windows 64-bit systems. Fix: Disconnect other USB serial devices. Avoid opening COM ports or serial terminal applications while programming. Try a different USB port with a direct connection instead of a USB hub. 3. Driver bugs or Quartus version mismatches. Driver bugs or Quartus version mismatches can prevent Quartus Programmer from detecting the cable. Known bad driver versions or incompatible Quartus releases can cause the Programmer to lose the cable or prevent the standalone Programmer from detecting it. Fix: Reinstall the driver from the Quartus installation folder. Try an older or known-stable driver version. Avoid mixing drivers from multiple Quartus versions. 4. USB hub or signal quality problems. USB hub or signal quality problems can cause the USB-Blaster II to disappear after use. This is reported more often with poor-quality hubs or legacy USB 1.0 hubs. Fix: Plug the USB-Blaster II directly into the PC. Avoid poor-quality or legacy USB 1.0 hubs. 5. Clone USB-Blaster hardware. Clone USB-Blaster hardware can be unstable due to timing issues, firmware quirks, or driver incompatibilities. Fix: Replace the clone USB-Blaster with a known-good cable. 6. Closing Quartus Programmer leaves the cable in a bad state. Closing Quartus Programmer can leave the JTAG server running. It can leave the device handle locked. It can trigger USB re-enumeration issues on the USB stack. When Quartus Programmer is reopened, it may not be able to reattach to the already claimed cable. Fix: Unplug and replug the USB-Blaster II. Kill lingering JTAG server or Quartus Programmer processes. Reboot the system if the cable is still not detected.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Design Space Explorer II Tool (DSE ll) stops sending new jobs to remote hosts after finishing an initial job run?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition software version 19.1 and earlier versions, you may experience that new jobs will not start on the remote hosts after an existing job has finished. The Design Space Explorer II Tool will not show an error or warning messages when this problem occurs. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition software version 19.1. Download and install Patch 0.33 from the appropriate link below. • Download the Quartus® II software version 19.1 patch 0.33 for Windows (.exe) • Download the Quartus® II software version 19.1 patch 0.33 for Linux (.run) • Download the Readme for the Quartus® II software version 19.1 patch 0.33 (.txt) This problem is fixed beginning with version 19.3 of the Intel® Quartus® Prime Standard Edition software.Why does IP generation fail for some IP cores in Intel® Quartus® Prime Standard 19.1?
Description Due to missing Perl libraries in the Intel® Quartus® Prime Standard Edition software version 19.1, you may see various errors when generating some Platform Designer IP Cores. Error and Info messages indicating missing Perl library: Error: " Failed to find modelu Error: qsys-generate failed with exit code 1 Info: Can't locate Getopt/Long.pm Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition software version 19.1. Download and install Patch from the appropriate link below. Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Windows (.exe) Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Linux (.run) Download the Readme for Intel® Quartus® Prime Standard 19.1 Patch 0.01 (.txt)Error:18496 The Output <name> in pin location <name> (pad_<number>) is too close to PLL clock input pin (<name>) in pin location <name> (pad_<number>)
Description Due to a problem in the Quartus® Prime software version 16.0 and earlier, you may see this fitter error when the MAX® 10 E144 package design is compiled on Windows OS with the following conditions: 1. Connected PLL signal (non-PLL input clock signal) to PLL input clock pin 2. Assigned output pin next to PLL input clock pin which is connected to PLL signal (non-PLL input clock signal) Resolution A patch is available to fix this problem in the Quartus Prime Standard edition software version 16.1. Download and install patch 0.01cb from the appropriate link below. Be sure to read the readme for additional information. Download the Quartus Prime Standard software version 16.1 patch 0.01cb for Windows (.exe) Download the Quartus Prime Standard software version 16.1 patch 0.01cb Readme (.txt) This problem is fixed in Quartus Prime Standard software version 16.1 Update 2.Are there functional or security updates for the Intel® Quartus® Prime Standard Edition Software version 20.1?
Description The Intel® Quartus® Prime Standard Edition Software version 20.1 Patch 0.04std includes functional and security updates. Users should keep their software up-to-date and follow the technical recommendations to improve security. If additional security updates are needed, they will be provided in this article as they become available. Resolution A patch is available to include this update for the Intel® Quartus® Prime Standard Edition Software version 20.1. Download and install Patch 0.04std from the following links: Patch Intel® Quartus® Prime Standard Edition 20.1 Patch 0.04std for Windows (.exe) Patch Intel® Quartus® Prime Standard Edition 20.1 Patch 0.04std for Linux (.run) Readme for Intel® Quartus® Prime Standard Edition 20.1 Patch 0.04std (.txt) This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 21.1.FATAL: Cannot generate IP in a Windows environment!
Description Due to a problem in the Intel® Quartus® Prime Standard Edition software for Windows* version 19.1, you may see this error when generating any EMIF IP or Cyclone® V/Arria® V HPS IP. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 19.1. Download and install the patch from the appropriate link below. Download patch Intel® Quartus® Prime 19.1 Patch 0.02std for Windows (.exe) Download the Readme for Intel® Quartus® Prime 19.1 Patch 0.02std (.txt) This problem is fixed beginning with version 20.1 of the Intel® Quartus® Prime Standard Edition Software.Why does the Nios® V processor fail to generate HDL and report "Error: add_fileset_file" in the Quartus® Prime Standard Edition Software?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This problem is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl calls add_fileset_file on a simulator, which is not supported in Windows OS. The simulators are Cadence Simulator, Synopsys VCS*, and VCS MX. For information on the simulators' supported platforms, refer to Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators. Resolution To work around this problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, follow these steps: Navigate to the following hw.tcl files: <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_dbg_mod_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_timer_msip_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_g/intel_niosv_g_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_m/intel_niosv_m_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_c/intel_niosv_c_unit_hw.tcl Inside each hw.tcl file, find set simulators [list ]. Modify the subsequent if-else statement to, set simulators [list ] if {$sim_synth == "sim" } { if { [file exists intelfpga] && [file isdirectory intelfpga] } { set simulators [list intelfpga] } elseif { $::tcl_platform(platform) == "windows" } { set simulators [list aldec mentor] } else { set simulators [list aldec cadence mentor synopsys] } } The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows* OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows* OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.