Why does the Nios® V processor fail to generate HDL and report "Error: add_fileset_file" in the Quartus® Prime Standard Edition Software?

Description

Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This problem is present only on Windows OS.

Example error message:

Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr”   

This is because the Nios® V processor hw.tcl calls add_fileset_file on a simulator, which is not supported in Windows OS. The simulators are Cadence Simulator, Synopsys VCS*, and VCS MX.

For information on the simulators' supported platforms, refer to Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.

Resolution

To work around this problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, follow these steps:

1. Navigate to the following hw.tcl files:
   • <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_dbg_mod_hw.tcl
   • <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_timer_msip_hw.tcl
   • <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_g/intel_niosv_g_unit_hw.tcl
   • <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_m/intel_niosv_m_unit_hw.tcl
   • <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_c/intel_niosv_c_unit_hw.tcl
2. Inside each hw.tcl file, find set simulators [list ].
3. Modify the subsequent if-else statement to,

This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.