Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Why does building the Nios® V software project fail in the network server that implements UNC paths?
Description Due to a software problem in Ashling RiscFree IDE for Quartus® Prime Pro Edition Software version 24.1 in dealing with the UNC path, you might see the below errors: ../riscv32-unknown-elf/bin/ld.exe: cannot find -lc: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lstdc++: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lgcc: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lm: Invalid argument collect2.exe: error: ld returned 1 exit status UNC path is used to access network resources and must be in the format specified by the Universal Naming Convention. Resolution Workaround: A patch is available to fix this problem for the Ashling RiscFree IDE for Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.01rf from the attached zip file. Zip file content: Patch 0.01rf for Ashling RiscFree 24.1 for Windows (.exe) Readme for Patch 0.01rf for Ashling RiscFree 24.1 for Windows (.txt) Related Information: File path formats on Windows systems - .NET | Microsoft Learn For more information on the difference between traditional DOS and UNC paths in Windows systems.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.
Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IPHow accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?
Description Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically: Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function. Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it. Resolution To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows: Incorrect Pin Index Correct Pin Index 10/11 0/1 22/23 12/13 34/35 24/25 46/47 36/37 Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner. This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Design Software versions prior to 25.3, placing both LVDS SERDES IP instances within the same IO sub-bank may not be successful. If you attempt to put the bytes of both IP instances in the same IO sub-bank, you may encounter the following fitter error: Error(14996): The Fitter failed to find a legal placement for all periphery components. Resolution This problem has been fixed in the Quartus® Prime Pro Edition Design Software Version 25.3. Use the Quartus Prime Pro Edition Design Software Version 25.3 to generate the LVDS SERDES IP and compile the project. If you must use the Quartus Prime Pro Edition Design Software versions prior to 25.3, please contact Support with this KDB link. Related Articles Can I distribute the channels of an Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? How many IOPLLs are used when implementing Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks?Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.WARNING: Tcl script <file name> error: Module "none" doesn't exist in SOPC design "nios_setup".
Description Due to a problem in the Quartus® II software, if you uncheck Enable for any driver in the Drivers tab of BSP Editor for Nios® II, export a tcl file, and specify it as an option of some command like nios2-bsp, you will get the tcl script error. Resolution To work around this problem, open the tcl file in a text editor and swap the 2 operand of set_driver command. For example, if you disable led_io driver, you will get a line below. set_driver led_io none Then modify the line like below. set_driver none led_io This problem is scheduled to be fixed in a future release of the Quartus II software.How do I include a C file in my Nios II C software project?
Description C2H doesn’t support generating accelerators from C files. There is a work-around which will enable you to call your accelerator(s) from a C program which involves moving the functions you wish to accelerate from a C source file to a C source file. Once your functions are in a C source file, the C2H compiler can effectively “see them” and convert them into hardware accelerators. There are some additional steps necessary for mixing C and C functions (and files). The GNU tool-chain supports the calling of C functions from C programs (and vice versa) through a well defined methodology of explicit assertion. The way this works is that, from your C program you tell the compiler which functions should be call as C functions- instead of C . This operation is done through the use of the extern “C” syntax within the C source file. Some examples of the extern “C” syntax in action are as follows: Calling C function from C program Setup: You have a function void bar(void), which lives in C source file “bar.c” that you want to call from the C source file “foo.cpp”. Solution: Add this to the top of “foo.cpp”- extern “C”void foo(void); Calling C functions from C program Setup: A collection of functions which lives in C source file “bar.c” that you want to call from the C source file “foo.cpp”. Solution: Simply add braces around the group of functions at the top of the extern statement in “foo.cpp”- extern “C” { void foo(void); int foo2(int number); int foo3(int number1, int number2); } Calling a C header from a C program Setup: You have a whole collection of C functions (or a library) in a file called “bar.c” that you want to call from your C program “foo.c”, and you really don’t want to list them individually through procedure #2 (above). You do have a header file for “bar.c” called “bar.h” which declares the interface to the functions. Solution: The extern statement also works for header files… In the file “foo.cpp”, use the extern statement to add the header file- extern “C” { #include “bar.h” } Which methodology is best to use with C2H? When using the C2H compiler, it is recommended that a user “isolate” the function for acceleration into its own file, so using the first example is the best approach for accelerating functions with the C2H compiler.How can I monitor the RY/BY pin of the AM29LV128 flash device on the Nios® development board, Stratix® II Edition from within my Stratix II application?
Description In order to use the RY/BY output of the flash device within a design running on the Nios development board, Stratix II Edition follow the instructions below: Add an input pin to the config_controller design located in the <Nios II install directory>\examples\<HDL>\<development board>\EPM7128_flash_config_controller directory. Assign the new input pin to location 35 on the EPM7128 device. Recompile the design in the Quartus ® II tool. The EPM7128 device will now tri-state its connection to the flash's RY/BY pin. Program the EPM7128 device on the Stratix II board with the POF file generated in the above step. Open the Quartus II design which you are targeting to the Stratix II board. Go to the Assignment Editor and add the "Weak Pull-up Resistor" option for the RY/BY pin. After performing the above steps you can access the RY/BY output of the flash in your Stratix II design.
