Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IP
How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?
Description Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically: Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function. Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it. Resolution To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows: Incorrect Pin Index Correct Pin Index 10/11 0/1 22/23 12/13 34/35 24/25 46/47 36/37 Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner. This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Design Software versions prior to 25.3, placing both LVDS SERDES IP instances within the same IO sub-bank may not be successful. If you attempt to put the bytes of both IP instances in the same IO sub-bank, you may encounter the following fitter error: Error(14996): The Fitter failed to find a legal placement for all periphery components. Resolution This problem has been fixed in the Quartus® Prime Pro Edition Design Software Version 25.3. Use the Quartus Prime Pro Edition Design Software Version 25.3 to generate the LVDS SERDES IP and compile the project. If you must use the Quartus Prime Pro Edition Design Software versions prior to 25.3, please contact Support with this KDB link. Related Articles Can I distribute the channels of an Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? How many IOPLLs are used when implementing Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks?Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.WARNING: Tcl script <file name> error: Module "none" doesn't exist in SOPC design "nios_setup".
Description Due to a problem in the Quartus® II software, if you uncheck Enable for any driver in the Drivers tab of BSP Editor for Nios® II, export a tcl file, and specify it as an option of some command like nios2-bsp, you will get the tcl script error. Resolution To work around this problem, open the tcl file in a text editor and swap the 2 operand of set_driver command. For example, if you disable led_io driver, you will get a line below. set_driver led_io none Then modify the line like below. set_driver none led_io This problem is scheduled to be fixed in a future release of the Quartus II software.How do I include a C file in my Nios II C software project?
Description C2H doesn’t support generating accelerators from C files. There is a work-around which will enable you to call your accelerator(s) from a C program which involves moving the functions you wish to accelerate from a C source file to a C source file. Once your functions are in a C source file, the C2H compiler can effectively “see them” and convert them into hardware accelerators. There are some additional steps necessary for mixing C and C functions (and files). The GNU tool-chain supports the calling of C functions from C programs (and vice versa) through a well defined methodology of explicit assertion. The way this works is that, from your C program you tell the compiler which functions should be call as C functions- instead of C . This operation is done through the use of the extern “C” syntax within the C source file. Some examples of the extern “C” syntax in action are as follows: Calling C function from C program Setup: You have a function void bar(void), which lives in C source file “bar.c” that you want to call from the C source file “foo.cpp”. Solution: Add this to the top of “foo.cpp”- extern “C”void foo(void); Calling C functions from C program Setup: A collection of functions which lives in C source file “bar.c” that you want to call from the C source file “foo.cpp”. Solution: Simply add braces around the group of functions at the top of the extern statement in “foo.cpp”- extern “C” { void foo(void); int foo2(int number); int foo3(int number1, int number2); } Calling a C header from a C program Setup: You have a whole collection of C functions (or a library) in a file called “bar.c” that you want to call from your C program “foo.c”, and you really don’t want to list them individually through procedure #2 (above). You do have a header file for “bar.c” called “bar.h” which declares the interface to the functions. Solution: The extern statement also works for header files… In the file “foo.cpp”, use the extern statement to add the header file- extern “C” { #include “bar.h” } Which methodology is best to use with C2H? When using the C2H compiler, it is recommended that a user “isolate” the function for acceleration into its own file, so using the first example is the best approach for accelerating functions with the C2H compiler.How can I monitor the RY/BY pin of the AM29LV128 flash device on the Nios® development board, Stratix® II Edition from within my Stratix II application?
Description In order to use the RY/BY output of the flash device within a design running on the Nios development board, Stratix II Edition follow the instructions below: Add an input pin to the config_controller design located in the <Nios II install directory>\examples\<HDL>\<development board>\EPM7128_flash_config_controller directory. Assign the new input pin to location 35 on the EPM7128 device. Recompile the design in the Quartus ® II tool. The EPM7128 device will now tri-state its connection to the flash's RY/BY pin. Program the EPM7128 device on the Stratix II board with the POF file generated in the above step. Open the Quartus II design which you are targeting to the Stratix II board. Go to the Assignment Editor and add the "Weak Pull-up Resistor" option for the RY/BY pin. After performing the above steps you can access the RY/BY output of the flash in your Stratix II design.Why does IP Upgrade fail on a composed IP that includes the discontinued Nios® II processor IP in future Quartus® Prime Software?
Description In the Quartus® Prime Pro Edition Software version 24.1, when migrating a composed IP that contains the discontinued Nios® II processor from the previous software version, the IP Upgrade feature reports the following error: “IP component no longer supported. Compilation of IP not supported in current software version.” This problem is due to the discontinued Nios® II processor. Resolution Workaround: Recommended action is to implement Nios® V processor IPs with equivalent functions in a new composed IP. Alternatively, add the following property in the *hw.tcl of the existing composed IP, set_module_property SUPPORTED_EOL_SUB_IPS {altera_nios2_gen2} The discontinued Nios® II processor IP core is render unavailable in the Quartus® Prime IP Catalog after the Last Time Shipments. Interested parties are encouraged to refer to the Nios II Processor Product Discontinuation Notice (PDN2312).Why do I see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the transceiver reconfiguration controller when using Stratix V, Arria V, or Cyclone V transceiver devices?
Description Due to a bug in the Quartus® II software version 13.0 and earlier, you may see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the reconfiguration controller when using Stratix® V, Arria® V, or Cyclone® V transceiver devices. When accessing the following transceiver PMA functions through the reconfiguration controller Avalon memory mapped interface using a NIOS II master or other Avalon master you may encounter a failure in the transceiver PMA. Stratix V GX/GT/GS, Arria V GZ Arria V GX/GT/ST/SX Cyclone V GX/GT/ST Pre and post CDR reverse serial loopback Pre and post CDR reverse serial loopback Pre and post CDR reverse serial loopback - Rx equalization Rx equalization The PMA failure is caused by corruption inside the reconfiguration controller if the reconfig_mgmt_address bus toggles when the reconfig_busy signal is asserted. The failure can be recovered by reprogramming the FPGA. Resolution To work around the problem, you can insert logic that prevents toggling of the reconfiguration controller reconfig_mgmt_address bus when the reconfig_busy signal is asserted. Or you can replace the "alt_xreconf_uif.sv" file that resides in your Reconfiguration Controller Megawizard™ generated <instance_name> folder with this file and recompile your design. This problem will be fixed in a future version of the Quartus II software.Why does nios2-bsp fail to look for .sopcinfo file when .ipx is used?
Description Due to a problem in the Quartus® Prime Pro software version 17.0, when using an .ipx file to create multiple custom components, the .sopcinfo file is generated in the qsys_name folder and not in the project directory folder. When you are building a Nios® II application and bsp project in the Nios II Software Build Tools, you will see an error when you build the application project. Error: Info: Compiling ../src/main.c to obj/default/main.o nios2-elf-gcc -xc -MP -MMD -c -I../bsp/HAL/inc -I../bsp -I../bsp/drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -O2 -g -Wall -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global -o obj/default/main.o ../src/main.c ../src/main.c:33:38: fatal error: custom_pattern_generator.h: No such file or directory #include "custom_pattern_generator.h" ^ compilation terminated. make: *** [obj/default/main.o] Error 1 make: Leaving directory Resolution To workaround this problem, copy the qsys_name.sopcinfo file in the qsys_name folder into the project directory which has the same path with where the <component name>.ipx file is located and rebuild the application file in the Nios II Software Build Tools. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro software
