Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.1 SP1?
Description There is a single patch available to address known software issues for Stratix® V, Arria® V, and Cyclone® V devices in the Quartus® II software version 12.1 SP1. This patch will be updated periodically with the latest software fixes. Check here periodically for updated files. You can refer to the readme file for the date the file was updated and a list of software fixes. Resolution Download and install the Stratix V/Arria V/Cyclone V device patch 1.dp7 from the appropriate link below. You must install the Quartus II software version 12.1 SP1 before installing this patch. Note that you should not install any non-Stratix V/Arria V/Cyclone V patches on the Quartus II software version 12.1 SP1 after installing this patch. Patch 1.dp7 includes all the fixes from previously-released patches. You can install 1.dp7 over the previous device patches, but you do not need to install the previous device patches before installing 1.dp7. For Windows, users must install both part 1 and part 2 to apply all fixes for patch 1.dp7. For Linux, the single patch contains all fixes for patch 1.dp7. Download the version 12.1 SP1 patch 1.dp7 part 1 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp7 part 2 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp7 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp7 (.txt) To install a previously-released version of the Quartus II software version 12.1 SP1 Stratix V/Arria V/Cyclone V device patch, select the appropriate link below. Device patch 1.dp1 Download the version 12.1 SP1 patch 1.dp1 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp1 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp1 (.txt) Device patch 1.dp4 Download the version 12.1 SP1 patch 1.dp4 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp4 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp4 (.txt) Device patch 1.dp6 Download the version 12.1 SP1 patch 1.dp6 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp6 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp6 (.txt) Related Articles Errata - Known Stratix V timing model issues in Quartus II software version 12.1 SP1 The .qip/.sdc files in the project .qsf are reordered when opening a project or re-generating IP in the Quartus II software version 12.1 SP1. Why is the dedicated transceiver refclk pin Vicm lower than the specification in the Arria V GX device datasheet when using Quartus II software versions 12.1sp1 and earlier? Error (170208): Cannot place <X> nodes into a single ALM Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen5_postproc.cpp, Line: 266 Internal Error: Sub-system: FSAC, File: /quartus/fitter/fsac/fsac_clkbuf_fix_atom_netlist.cpp, Line: 1698Error (10232): Verilog HDL error at bitec_dp_rx_ss_audio.v(420): index 64 cannot fall outside the declared range [63:0] for vector "fifo_data_x2chan_mux"
Description Due to a problem in the Quartus® II software version 14.0, you may see this error when compiling a design that contains the DisplayPort IP that has more that 2 Audio receive channels enabled. Resolution To work around this problem in the Quartus® II software version 14.0, replace the existing file <IP variation name>/bitec_dp/rx/ss/bitec_dp_rx_ss_audio.v with the attached version of this file. bitec_dp_rx_ss_audio.v This problem has been fixed starting in the v14.1 release of the Quartus® II software.Why does Design Space Explorer only show two effort levels for performance optimization?
Description Due to a problem in the Quartus® II software version 12.0 SP2 and earlier, Design Space Explorer (DSE) may only show two available effort levels when optimizing for performance. There should be five available effort levels. This problem affects designs targeting Arria® V, Cyclone® IV, and Cyclone V devices. Resolution To fix this problem, download and install patch 2.19 from the links below. For designs targeting Arria V or Cyclone V devices, this fix is also included in device patch 2.dp3 or later from the related solution below. You must install the Quartus II software version 12.0 SP2 before installing either of these patches. Download the version 12.0 SP2 patch 2.19 for Windows (.exe) Download the version 12.0 SP2 patch 2.19 for Linux (.tar) Download the Readme for the Quartus II software version 12.0 SP2 patch 2.19 (.txt) This problem is fixed beginning with the Quartus II software version 12.1. Related Articles How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.0 SP2?Why does it take several seconds for Active Serial (AS) configuration to complete after power-up of the Cyclone V GT FPGA development kit?
Description Due to the design of the system controller in the MAX® V device, AS configuration is delayed for several seconds after power-up of the Cyclone® V GT FPGA development kit. This delay may cause a problem if your design uses PCI Express (PCIe) and AS configuration mode, as this delay may result in not meeting the PCIe wake-up time requirement. Resolution To reduce the delay of AS configuration in the Cyclone V GT FPGA development kit, program the MAX V device with this Programmer Object File (.pof ) file: max5.pof. You can also use this Quartus® II project: max5_CVGT_devkit_AS.zip for the design in the MAX V device. Related Articles How do I access the EPCQ configuration device on the Cyclone V GT FPGA Development Kit?Why do I see hold time violations in Triple Speed Ethernet IP Core with Quartus II v15.0?
Description Due to a problem in Quartus® II software version 15.0, you may see marginal hold time violation especially in multi-channel Triple Speed Ethernet IP Core designs that target Arria® V, Arria® 10 , Cyclone® V and Stratix® V device families. Resolution To work around this issue, add the following Synopsys Design Constraint file (.sdc) constraints for Fitter into your project SDC file. if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] 0.0ns } else { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] <value> } *Note: Increase the “<value>” from “0.1ns” to “0.2ns” if the hold time violation persisted. Refer to “Table 2-2: Recommended Quartus II Pin Assignments” in Triple-Speed Ethernet MegaCore Function User Guide for other related recommendations. For TSE IP with IEEE 1588v2 feature enabled and target Arria V device family, apply the following patch in addition to the workaround above: Please download the appropriate Quartus® II software version 15.0 patch 0.14 from the following links: Download the version 15.0 patch 0.14 for Windows (.exe) Download the version 15.0 patch 0.14 for Linux (.run) Download the Readme for the Quartus II software version 15.0 patch 0.14 (.txt) This is scheduled to be fixed in a future release of the Quartus II software.How do I stitch multiple MIF files generated by the Quartus II software into a single MIF file, for fPLL reconfiguration in Stratix V, Arria V and Cyclone V devices?
Description You can stitch multiple Memory Initialization Files (MIF) generated by Quartus® II software into a single MIF file for fPLL reconfiguration in Stratix® V, Arria® V and Cyclone® V devices using the script provided in the link below: merge_mif.tcl To use the script, follow the steps below: 1. Place the tcl file and the MIF files in the same folder. 2. Source the merge_mif.tcl in tcl console. 3. Type the following command to stich 2 mif files (e.g A.mif and B.mif) into output.mif. Command : stitch A.mif B.mif [output.mif] Note : If you do not specify the optional [output.mif] paramater, it defaults to merged.mif. 4. In merged.mif, the content of B.mif comes after A.mif. 5. Repeat step 3 if you want to merge another MIF file (e.g C.mif) to merged.mif . You can stitch multiple MIF files together as long as the depth of the merged file does not exceed 512. Refer to AN661 : Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions (PDF) for more information on performing PLL reconfiguration via MIF streaming.Error (272006): Invalid setting: NUMBER_OF_MULTIPLIERS is greater than 1 for PREADDER_MODE=INPUT
Description Due to a problem in the Quartus® II software version 11.0 and later, you may see this error when compiling designs targeting Stratix® V, Arria® V, and Cyclone® V devices. This error occurs if you used the MegaWizard™ Plug-In Manager to create an ALTMULT_ADD megafunction with 2 or more multipliers and preadder mode selected as Input. Resolution To work around this problem, use HDL code to infer the required functionality. A VHDL example for sum-of-two multipliers with preadder is provided below. This example may be modified to support other configurations. Additional templates are available within the Quartus II Text Editor. For further information, see Recommended HDL Coding Sytles (PDF) in the Quartus II Handbook. preadder_input.vhd This problem is fixed beginning with the Quartus II software version 12.0.Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 621 Bad mask!
Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a Cyclone® IV or Cyclone V design using the Functional Safety Separation Flow. During partition import of strictly preserved safety partitions, routes to top-level safe IO buffers are not correctly preserved. When the Assembler detects the preservation mismatch during the Design Modification Flow it fails with this internal error. Resolution To work around this problem, for the Quartus II software version 13.1 Update 4, download and install patches 4.30 and 4.55 from the links below. You must install the Quartus II software version 13.1 Update 4 before installing these patches. Download the Quartus II software version 13.1 Update 4 patch 4.30 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.30 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.30 (.txt) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.55 (.txt) For the Quartus II software version 14.1 Update 1, download and install patch 1.04 from the links below. You must install the Quartus II software version 14.1 Update 1 before installing this patch. Download the Quartus II software version 14.1 Update 1 patch 1.04 for Windows (.exe) Download the Quartus II software version 14.1 Update 1 patch 1.04 for Linux (.run) Download the Readme for the Quartus II software version 14.1 Update 1 patch 1.04 (.txt) This problem is fixed beginning with version 15.0 of the Quartus II software.