ERROR building simple NIOSV Compact project

Hello and greetings All Quartus + NIOSV experts, or indeed anybody who can help me fix this error !

I am trying to build a System Verilog design, based on Platform Designer, which uses a NIOSV compact IP core. 

I am using Quartus Prime Version 25,1 Standard Edition on a Windows 10 Machine.

When trying to compile my test design i get these 2 errors :

Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'";  expecting ":", or "?", or binary operator. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10112): Ignored design unit "niosv_cpp_fsm" at niosv_cpp_fsm.sv(18) due to previous errors

Error 10112 is caused by previous error 10170. Does anybody have an idea why i get these errors ? I can't see the offending SV code because its encrypted (of course!). Is there a fix as well for this problem ?

Thanks for any help,

Dr Barry H