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drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
9 months ago
Solved

ERROR building simple NIOSV Compact project

Hello and greetings All Quartus + NIOSV experts, or indeed anybody who can help me fix this error ! I am trying to build a System Verilog design, based on Platform Designer, which uses a NIOSV compa...
Embedded Applications Layer
Nios Architecture
Nios Cpu
  • Archer_Altera's avatar
    Archer_Altera
    9 months ago

    Hi Barry,

    Rather than Adding QSYS into project, please add QIP into the project. From 25.1std, the tool supports QIP only due to a change in Quartus compiler. 

    The tool also prompts with message below. 

     

    You may find a qip file located in the same folder of qsys system top level hdl file under project directory liking this.

    Hope this is helpful.

    Archer_Altera

Archer_Altera's avatar
Archer_Altera
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi Barry,

I can reproduce the issue you met on my side.

This needs time for us to find the root cause. I will let you know when there is progress about this.

Regards,

Archer_Altera

  • drbarryh's avatar
    drbarryh
    Icon for Contributor rankContributor
    9 months ago

    Hi Archer_Altera, Thanks for your quick reply and analysis. Do you think it could be a tool installation problem ? Or a tool version issue ? Maybe other Standard editions don't have this problem ? I don't know yet because i have only managed to install the latest version of Standard edition.

    Thanks,

    Barry

    • Archer_Altera's avatar
      Archer_Altera
      Icon for Occasional Contributor rankOccasional Contributor
      9 months ago

      Hi Barry,

      Rather than Adding QSYS into project, please add QIP into the project. From 25.1std, the tool supports QIP only due to a change in Quartus compiler. 

      The tool also prompts with message below. 

       

      You may find a qip file located in the same folder of qsys system top level hdl file under project directory liking this.

      Hope this is helpful.

      Archer_Altera

      • drbarryh's avatar
        drbarryh
        Icon for Contributor rankContributor
        9 months ago

        Hi Archer,

        Thanks for the tips !

        I did see that step but i my may have forgotten to do that initially. Now i have done that and when i look into the FILES included in my project (which is called readout_fpga)  i can see that i have added both a readout_fpga.qsys file and a readout_fpga.qip file from the synthesis directory. Is that correct ? Or should i delete the qsys file as it may cause confusion and just leave the qip file in my project ?

        Thanks,

        Barry