Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv
Description Due to a problem in the JTAG-Over-Protocol Intel® FPGA IP, using the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 you may see an error message similar to the following when generating the HDL code with the option Create simulation model= Verilog or VHDL. Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv while executing "add_fileset_file $current_sim/intel_st_dbg_if_csr_h.sv SYSTEM_VERILOG PATH $current_sim/intel_st_dbg_if_csr_h.sv $attr" (procedure "add_rtl_files" line 25) invoked from within "add_rtl_files sim" (procedure "sim_callback" line 2) invoked from within "sim_callback intel_st_dbg_if_top" Resolution A patch is available to work around this problem for the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2. Download and install the patch from the appropriate link below. Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 (.txt) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.Why does the DisplayPort IP design example fail to generate a programming file when using the Quartus® Prime Pro Edition Software v19.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software v19.1, designs that use the Nios® II/e processor core without a valid Nios® II processor license will fail to generate programming files even though the design compilation is successful. The DisplayPort IP design example uses the Nios II/e processor core. Hence, it will be impacted by this problem. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v19.1, install the patch 0.02 below and regenerate the DisplayPort IP design example: This problem is fixed starting with the Quartus Prime Pro Edition Software v19.2.Why doesn’t Arria10 GX development board documentation BOM match the schematic?
Description The downloaded zip file (arria10GX_10ax115sf45_fpga_v15.1.2) for Arria® 10 GX FPGA Package (Production Edition) contains schematic file (A10GX_PCIE_E3p1) and BOM file (A10_PCIe_RevE3p1_Agile_BOM_RevEN100A). BOM does not match the schematic. Here is the correct BOM file: a10_fpga_devkit_reve3p1_agile_bom_rev0g.xlsWhy does the Intel® Quartus® Prime Timing Analyzer ignore the timing constraints for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express*?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2 and earlier, the Intel® Quartus® Prime Timing Analyzer will ignore the timing constraints for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* if you have a generate statement used in your VHDL or Verilog code to create the IP in your design. This problem occurs because the generate statement will create a “\” as the hierachy path that is not recognized by the Intel Arria 10/Cyclone 10 Hard IP for PCI Express* SDC (Synopsys* Design Constraint) files. Resolution To work around this problem, download the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* SDC file and replace the altera_pci_express.sdc in <project_name>/<pcie_name>/altera_pcie_a10_hip/synth. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.3.Why does my Arria 10 SoC industrial grade device fail to boot at low temperature?
Description Certain Hard Processor System (HPS) PLL clock output frequencies require a specific programming setup sequence to ramp the PLL frequency gradually in Arria 10 SoC industrial grade devices at -40degreesC, otherwise the HPS may fail to boot. Resolution To workaround this issue in SoC EDS software version 16.0, download the patch below and follow the instructions in the readme. Download the SoC EDS software version 16.0 Patch 002soc for Linux(.run) Download the Readme for SoC EDS software version 16.0 Patch 002soc for Linux(.txt) The corresponding patch for socfpga UEFI is available in the rel_socfpga_arria10_soceds_16.0 tag of the socfpga_udk2015 branch from the github repository: https://github.com/altera-opensource/uefi-socfpga. This problem is scheduled to be fixed in a future version of the SoC EDS software.Why is an user output pin in an unexpected state during initialization stage in Intel® Arria® 10 device?
Description You may see user output pins go into an unexpected state during initialization stage in Intel® Arria® 10 device. This is because user logic and user I/O pins are activated gradually, not at the same time during initialization stage. An example is shown below. ( Figure of example ) An user input pin connects to the low active set port of a register. This user input pin is kept low from power-up to user mode. A data output port from the register connects to an user output pin. The user output pin is expected to keep high, because the user I/O pins are in input tri-state with weak pull-up during configuration stage and initialization state and the register is expected to be set to high by the set port in user mode. But use logic and user I/O pins are activated gradually during initialization stage. When the register and the user output pin are activated faster than the input port and the initial state of the register is low, the output pin propagates low from the register until the input port is activated and the set port of the register becomes low. When an external device monitors an output from the Intel Arria 10 device, an unexpected state during initialization stage may affect the behavior of the external device. Resolution To work around this problem, use one of the following ways. Workaround 1: Make the external device to ignore the state of the user output pin until INIT_DONE pin goes high (Figure of workaround 1) Workaround 2: Keep the input state to the external devices proper using external logic until INIT_DONE pin goes high (Figure of workaround 2) Workaround 3: Keep the output state of the Arria 10 device using user logic until internal INIT_DONE signal goes high (Figure of workaround 3) You can use internal INIT_DONE signal with the following WYSIWYG instantiation. << Verilog >> twentynm_controller u1 ( .initdonecore(<internal INIT_DONE wire name>) ); << VHDL >> component twentynm_controller is port( initdonecore: out STD_LOGIC ); end component; u1 : twentynm_controller port map( initdonecore => <internal INIT_DONE wire name> );Is early I/O release on Arria 10 SOC supported in SoC EDS 16.0?
Description The early I/O release feature for Arria®10 is not supported in the standard release of SoC Embedded Design Suite (SoC EDS) software version 16.0. Therefore, the peripheral_rbf_filename and core_rbf_filename fields in the SoC EDS bsp-editor tool are greyed out and replaced with a single rbf_filename field. The early I/O release flow: In the early I/O release flow, all I/O are configured and the HPS shared I/O and hard memory controller I/O are released so that the HPS has immediate access to them. At a later time, the FPGA fabric is configured and the FPGA I/O are released and available to the user design. Resolution To enable the early I/O release feature in SoC EDS software version 16.0, download the patches below and follow the instructions in the readme.txt. Download the SoC EDS software version 16.0 Patch 002 for Linux(.run) Download the Readme for SoC EDS software version 16.0 Patch 002 for Linux(.txt) Download the SoC EDS software version 16.0 Patch 004 for Linux(.run) Download the Readme for SoC EDS software version 16.0 Patch 004 for Linux(.txt) This feature is scheduled to be supported in a future version of the SoC EDS software.