Why does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346Why is there "sopcinfo2swinfo.exe: command not found" when running sopc-create-header-files under WSL, or Docker under Windows?
Description An error message like this: sopc-create-header-files: line 182: sopcinfo2swinfo.exe: command not found sopc-create-header-files: sopcinfo2swinfo.exe --input=./peripheral_subsys.sopcinfo --output=/tmp/sopc-create-header-files.1312.tmp.swinfo failed will be seen in the Quartus ® Prime Pro Edition Software version 25.3.1 and earlier, when using the sopc-create-header-files script within the Linux version of the Quartus ® Prime Pro Edition Software, running on the Microsoft* Windows operating system. The Linux version of the tools can be installed under Windows* using WSL, WSL2 or Docker. In all of these cases, the sopc-create-header-files script detects that it is running under Windows* and looks for an internal tool with the suffix “.exe”. However, since the Linux version has been installed, the tool does not have that suffix and so cannot be found by the sopc-create-header-files script. Resolution To work around the problem, either switch to using a Windows* installation of the Quartus® Prime Pro Edition Software, or follow these steps to continue using the Linux installation under Windows*: Under Linux, use the command “which sopc-create-header-files” to find the location of the script. Copy the script from this location to another location of your choice. Make the newly copied script version writable using the command: chmod +w <path to newly copied script> Modify your newly copied script version. Find the following line: windows_exe=.exe and either remove it or add a single # symbol at the start to comment it Use your newly modified version of the script instead of the installed version. This will now execute correctly.Why do I get the error Internal Error "No Active Family" when trying to generate a programming JAM file via command line "quartus_pfg"
Description When trying to generate a JAM programing file (.jam) via the quartus_pfg command line from a Chain Description File (.cdf). quartus_pfg -c <file>.cdf <file>.jam You may get the following error message: Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_jam.cpp, Line: 2873 No Active Family Stack Trace: Quartus 0x3cce3e: PGMIO_JAM::jam2_filter(int, PGMIO_JTAG_UNI_ENGINE*, std::basic_ifstream >&, std::ostream&) + 0x582 (pgm_pgmio) Quartus 0x3d0a7a: PGMIO_JAM::jam2_create_file(int, PGMIO_JTAG_UNI_ENGINE*) + 0x846 (pgm_pgmio) Quartus 0x3d4ec2: PGMIO_JAM::create_output_file(std::vector >*, FIO_PATH const&, bool) + 0x3e8c (pgm_pgmio) This error may be due to an issue were the source programming files on the .cdf file not being valid. Resolution To work around this problem, verify your programing source file or files with the following command line: quartus_pfg -i <source>.sof This command will help you determine if your source file or files are valid and invalid and provide additional info on the issues with the invalid files for troubleshooting. Replace the invalid files with valid ones once identified.Why does the Synchronous FIFO Parameterizable Macro (sync_fifo) incorrectly output all zeroes data after being empty?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 or earlier, you might see that the first output data from the FIFO after the FIFO has been empty is incorrectly set to zero. This problem occurs when using the Synchronous FIFO Parameterizable Macro (sync_fifo) in show-ahead mode. Resolution To work around this problem, instantiate the FIFO FPGA IP instead of the Synchronous FIFO Parameterizable Macro. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does Ashling* RiscFree* IDE for Altera* FPGA software reports unresolved inclusion warnings, despite a successful build of Nios® V processor software project?
Description Due to a problem in multiple versions of Ashling* RiscFree* IDE for Altera® FPGA, the unresolved inclusion warning might occur for any Nios ® V processor software projects. Note that, the warning is harmless. The affected software project will still build successfully. This is caused by a bug in the Indexer of Ashling* RiscFree* IDE, which fails to search for the relevant project files. The affected Ashling* RiscFree* IDE for Altera FPGA are: Software version v25.1.1 (dated as 31 st Jan 2025) Software version v25.2.1 (dated as 9 th May 2025) Software version v25.3.1 (dated 1 st August 2025) Resolution This problem is currently scheduled to be resolved in future release of Ashling* RiscFree* IDE for Altera FPGA software version v26.1.0 (dated as 19 th Dec 2025). Meanwhile, you may safely ignore this warning, as it does not affect the functionality of your project. If needed, please refer to the related article for the recommended workaround. Related Article: Ahsling RiscFree IDE 25.1.1: Unresolved inclusion | Altera CommunityError: Unknown option: -port_type while execute set_instance_assignment with the option
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see this error when running a "set_instance_assignment" with -port_type option e.g. Error:Unknown option: -port_type Error:--------------------------------------------------------------------------- Error:Usage: set_instance_assignment [-h] [-help] [-long_help] [-comment <comment>] [-disable] [-entity <entity_name>] [-fall] [-from <source>] -name <name> [-remove] [-rise] [-section_id <section id>] [-tag <data>] [-to <destination>] [<value>] Error: -h: Quick usage Error: -help: Short help Error: -long_help: Long help with examples and possible return values Error: -comment <comment>: Comment Error: -disable: Option to disable assignment Error: -entity <entity_name>: Entity to which to add assignment Error: -fall: Option applies to falling edge Error: -from <source>: Source of assignment Error: -name <name>: Assignment name Error: -remove: Option to remove assignment Error: -rise: Option applies to rising edge Error: -section_id <section id>: Section id Error: -tag <data>: Option to tag data to this assignment Error: -to <destination>: Destination of assignment Error: <value>: Assignment value Error:--------------------------------------------------------------------------- Error: while executing Error:"set_instance_assignment -name DUPLICATE_SYNC_FANIN …" Resolution A patch is available to fix this problem in the Quartus® Prime Pro Edition Software version 25.3. Download and install patch 0.24 below This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Error: invalid command name "else"
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see the error messages below when generating a VHDL simulation model in Platform Designer that includes the Remote Update IP. Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Resolution To work around this problem, generate Verilog Simulation Model for Remote Update IP. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Related IP Remote Update IP
