Why doesn't the IOPLL dynamic phase shift feature work on Arria® 10 FPGA and Cyclone® 10 GX FPGA devices?
Description You may see that the IOPLL dynamic phase shift feature does not work as expected in Arria® 10 FPGA and Cyclone® 10 GX FPGA devices when both “access to dynamic phase shift ports” and “dynamic reconfiguration of PLL” options are enabled in the IOPLL FPGA IP. This is because the IOPLL FPGA IP does not simultaneously support the dynamic reconfiguration and the direct phase shift feature. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 24.2.Why does my transceiver RTL simulation fail to assert rx_is_lockedtodata when in internal serial loopback with Stratix 10 L/H-Tile, Arria® 10, and Cyclone® 10 GX devices?
Description An undefined “x” signal on the transceiver rx_serial_data port may cause the rx_is_lockedtodata signal to fail to assert when performing RTL simulation of Stratix® 10 FPGA L/H-Tile, Arria® 10 FPGA, and Cyclone® 10 GX FPGA devices. Resolution To perform RTL simulation of transceiver internal serial loopback, ensure that a defined state of ‘0’ or ‘1’ is applied to the transceiver rx_serial_data port in your testbench. This prevents “x” propagation into the simulation model. The ‘0’ or ‘1’ from the rx_serial_data port will be ignored when the transceiver internal serial loopback switch is enabled.
Error(24244): Found an error when generating the IBIS Output File for board analysis
Description Due to a problem is Quartus® Prime Pro Edition Software version 25.3, you might see this error when generating this IBIS files. This problem only occurs on Windows* OS. This problem occurs because the quartus_py.exe file has changed location in the installation directory but the IBIS writer still calls the file from the previous location. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why is no display output observed when using the VVP-Full Design Example version 24.2 in the Arria® 10 FPGAs?
Description Due to problems porting the Nios® II Processor design to the Nios® V Processor design in the Quartus® Prime Pro Edition Software version 24.2, the Arria® 10 FPGA VVP-Full Design Example does not work correctly; no output is displayed. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see hold timing violations during Timing Analyzer when using the SPI (4 Wire Serial) IP. The SPI IP generates an SDC file that includes the following incorrect constraint: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This constraint can cause hold timing violations between the spi_gen_clk and the external clock, making timing closure difficult—especially in designs with multiple SPI instances. This problem does not occur in the Quartus® Prime Standard Edition Software, where such an SDC constraint is not generated for the SPI IP. Resolution To work around this problem: Remove the incorrect constraint from the IP-generated SDC file: Delete the following line: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why do I get a fatal error when I have a wildcard in my Nodefinder search?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, you might see a fatal error when searching in the Nodefinder launched from the Signal Tap Logic Analyzer. The error mostly occurs when the Nodefinder searches for a wildcard in the Named path at the hierarchy level where an encrypted IP is instantiated. Resolution This problem has been fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex® 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows* and Linux* below This patch ensures the transmitter maintains negative running disparity for Agilex® 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1.Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software versions 24.3.1, 25.1, and 25.1.1, and Quartus® Prime Standard Edition Software version 24.1. When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3 and Quartus® Prime Standard Edition software version 25.1.Internal Error: Sub-system: RDB, File: /quartus/db/rdb/rdb_utility.cpp, Line: 1944 rval == nullptr
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see this internal error when performing an IP Upgrade. Resolution To work around this problem, delete the qdb folder before compiling the project. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Is there any problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices?
Description No, there is no problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices. Leakage can occur between VCC and VCCIO as well as between VCC and VCCPT, which can cause both VCCIO and VCCPT to float up to a maximum approximation of 0.8V before the power supply is ramped up and after the power supply is ramped down. This is expected behavior, and if the power-up and power-down sequences are followed, it will neither cause any functional failure nor concern the device's reliability. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down. Resolution This is an expected behavior and will neither cause any functional failure nor reliability concern to the device if the power-up sequence and power-down sequence are followed. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down.
