Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv

Description

Due to a problem in the JTAG-Over-Protocol Intel® FPGA IP, using the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 you may see an error message similar to the following when generating the HDL code with the option Create simulation model= Verilog or VHDL.

Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv

    while executing

"add_fileset_file $current_sim/intel_st_dbg_if_csr_h.sv       SYSTEM_VERILOG PATH $current_sim/intel_st_dbg_if_csr_h.sv $attr"

    (procedure "add_rtl_files" line 25)

    invoked from within

"add_rtl_files sim"

    (procedure "sim_callback" line 2)

    invoked from within

"sim_callback intel_st_dbg_if_top"

Resolution

A patch is available to work around this problem for the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2.  Download and install the patch from the appropriate link below.

Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Windows (.exe)

Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Linux (.run)

Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40  (.txt)

Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Windows (.exe)

Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Linux (.run)

Download the Readme for Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13  (.txt)

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.