Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why does Quartus® Prime Pro Edition Installer for software version 25.3 install an older version of Ashling* RiscFree* IDE for Altera® (version dated 31st Jan 2025)?
Description Due to a problem in the Quartus ® Prime Pro Edition Installer for software version 25.3, it installs an older version of Ashling* RiscFree* IDE for Altera ® software. For example: Quartus ® Prime Pro Edition software version 25.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Quartus ® Prime Pro Edition software version 25.1.1 is paired with Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025). However, Quartus ® Prime Pro Edition software version 25.3 is paired with Ashling* RiscFree* IDE for Altera ® v25.1.1 (dated as 31 st Jan 2025). Thus, an older Ashling* RiscFree* IDE for Altera software is installed. This is because the installer is incorrectly packaged with the older software. Resolution To work around this problem in the Quartus ® Prime Pro Edition software version 25.3, please download the Ashling* RiscFree* IDE for Altera ® v25.2.1 (dated as 9 th May 2025) separately from the Quartus ® Prime Pro Edition Installer for software version 25.1.1. And use it with the Quartus ® Prime Pro Edition software version 25.3 for your project. You may follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select the appropriate Operating System. Download the Quartus® Prime Pro Edition Installer. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and ToolsWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for SimulationError: Unknown device part 10AX115S2F45I1SG
Description Due to a problem in the FPGA SDK for OpenCL™ version 21.1, this error may be seen when compiling an Arria® 10 OpenCL kernel using the flat flow. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 21.1. Download and install Patch 0.14cl from the files below. This problem is fixed starting with the Quartus® Prime Pro Edition software version 21.2.Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Error (16045): Instance "ccip_std_afu|bsp_logic_inst|board_inst" instantiates undefined entity "board" File: /home/anchen/Downloads/dla/build/dla/build/bsp_logic.sv Line: 133
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1.1, this error may occur when you compile the dla2019r1 source code. Resolution To work around this problem, please modify the build.sh file and add the below environment variable to line 175 export QUARTUS_ROOTDIR_OVERRIDE="$QUARTUS_ROOTDIR" This problem has been fixed in dla2019r3.
