Have the Arria® 10 PCI Express* Testbench required simulation files changed in version 24.2 of the Quartus® Prime Design Software?
Description Yes, as part of the ongoing improvements and streamlining of the Quartus® Prime Design Software core device family models (altera_mf etc.) the PCI Express* link-partner root-port BFMs that shipped as part of the altera_pcie_a10_tbed (IP version 19.1) were updated starting in version 24.2 to use Arria® 10 FPGA based primitives rather than the previously used Stratix® II FPGA primitives without a corresponding IP version increase. Attempting to use device libraries compiled from newer versions of Quartus® Prime Design Software with a testbench generated from an older version of the Quartus® Prime Pro software may lead to runtime errors from simulators about invalid module parameters of the form: Error! Unknown INTENDED_DEVICE_FAMILY=Stratix II. Resolution To resolve this problem, it is recommended to always re-generate Altera IP with the same version of the Quartus® Prime Pro software being used.Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the assembler fail to run after the update_mif flow?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.4, you may see this failure when running the assembler for Intel® Arria® 10 designs after running the update_mif flow using the following command: quartus_cdb <project name> --update_mif. Resolution To work around this problem, use the followng alternative flow to update your mif files. Enable the "Enable intermediate snapshot" in Assignment -> Settings -> Complier Settings Update the Memory Initialization file Run the quartus_fit --finalize instead of quartus_cdb --update_mif This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 20.1CMake Error: LIBUDEV_LIBRARIES variables are used in this project, but they are set to NOTFOUND.
Description When you build the Open Programmable Acceleration Engine (OPAE) SDK source code using a development branch and pack it into several local RPM packages, the following error might occur: CMake Error: The following variables are used in this project, but they are set to NOTFOUND. Please set them or make sure they are set and tested correctly in the CMake files: LIBUDEV_LIBRARIES linked by target "fpgaperf_counter" in directory /home/diankun/opae-sdk/external/opae-legacy/tools/fpgaperf_counter -- Configuring incomplete, errors occurred! See also "/home/XXX/opae-sdk/build/CMakeFiles/CMakeOutput.log". See also "/home/XXX/opae-sdk/build/CMakeFiles/CMakeError.log". Resolution To work around this problem, you should add “-DOPAE_LEGACY_TAG=<tag>” and “-DOPAE_SIM_TAG=<tag>” into your compile command. eg: cmake .. -DCPACK_GENERATOR=RPM -DOPAE_BUILD_LEGACY=ON -DOPAE_BUILD_EXTRA_TOOLS_FPGABIST=ON -DOPAE_BUILD_SIM=ON -DOPAE_LEGACY_TAG=2.0.10-2 -DOPAE_SIM_TAG=2.0.10-2Warning (16817): Verilog HDL warning at altera_xcvr_*_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_*_reconfig_parameters package
Description If your design contains multiple JESD204B IPs with different configurations, you may see the following warning in Intel® Quartus® Prime Pro software version 15.1 or later during Analysis and Synthesis stage. When targetting Intel Stratix® 10 devices: Warning (16817): Verilog HDL warning at altera_xcvr_rcfg_10_reconfig_parameters.sv: overwriting previous definition of module altera_xcvr_rcfg_10_reconfig_parameters When targetting Intel Arria® 10 or Intel Cyclone® 10 GX devices: Warning (16817): Verilog HDL warning at altera_xcvr_native_a10_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_native_a10_reconfig_parameters package If your design does not rely on the *_reconfig_parameters.sv package files for performing transceiver reconfiguration, it is safe to ignore the warning. Resolution If your design must include the reconfiguration packages, ensure the uniqueness of each of the packages by renaming the packages. For example, a design that contains two simplex RX interfaces with different data rates, assign a unique name by changing the package module from: package altera_xcvr_native_a10_reconfig_parameters; To: package altera_xcvr_native_a10_reconfig_parameters_inst1; In the first instance of RX, and changing to another unique name: package altera_xcvr_native_a10_reconfig_parameters_inst2; In the second instance of RX. Then, import those packages into your design per your design requirements.Why does the eCPRI IP assert mac_source_sop and mac_source_valid after the mac_source_ready is de-asserted?
Description Due to the ready latency of the eCPRI IP's mac_source_ready is 3 clock cycles, you may observe the mac_source_sop and mac_source_valid are asserted after the mac_source_ready is de-asserted. Resolution This is an expected behavior of the IP. This information has been updated in the eCPRI IP User Guide.Why is the input parallel termination value not shown in the Intel® Quartus® Prime fitter report for Input Pins and Bidirectional Pins?
Description Starting in the Intel® Quartus® Prime Pro Edition software version 19.3, input terminations using parallel OCT are reported in the Intel Quartus Prime Fitter > Plan Stage > Input Pins or Bidir Pins as Input Termination = ON. Previous Intel Quartus Prime Pro Edition software versions reported parallel OCT with the termination value. An example is Parallel 60 Ohm with Calibration. There is no workaround required as this is only a reporting issue. The parallel termination value is correctly set in the compiled project files with the value set in the Assignment Editor or in the case of EMIF IP as defined in the generated IP .qip file. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.When compiling an Intel® Cyclone® 10 FPGA design, why do I see the following Internal Error: Sub-system: FDI_DATA, File: /quartus/ddb/fdi/fdi_timing_model.cpp, Line: 753
Description Due to a problem with the Intel® Quartus® Prime Pro Edition Software v18.0, Intel® Cyclone® 10 GX FPGA designs might see the following Internal Error: Sub-system: FDI_DATA, File: /quartus/ddb/fdi/fdi_timing_model.cpp, Line: 753 during the fitter stage of compilation. This problem occurs when the Intel Cyclone 10 GX device family is installed without installing the Intel® Arria® 10 device family files. Resolution You are advised to install the Intel® FPGA Arria® 10 device family database file to work around this problem. This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 19.1.Why is my External Memory Interface (EMIF) IP preset file (.qprs) ignored after copying my project to a new location or using the Quartus® archiver?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you might see that your .qprs file is not taken into account when reopening the External Memory Interface (EMIF) IP after copying your project to a new location or using the Quartus® archiver. This problem is caused by using an absolute path within the External Memory Interface (EMIF) IP .ip file. Resolution To correctly read in the .qprs file, browse to the new location of the .qprs file from within the Platform Designer. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
