Why Arria® 10 SGMII Reference design in rocketboards.org doesn't work property?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software versions, you might see any errors with Arria® 10 SGMII Reference design on Arria® 10 SoC. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software version 20.3 or later, follow the steps below 1) Open attached script (run-cal-slack.tcl) 2) Edit instance name for GMII to SGMII converter in the run_cal_slack.tcl as below set EMAC0 sgmii_1 set EMAC1 sgmii_2 set EMAC2 null set EMAC3 null The script can support up to 4 ports. A variable should be set ‘null’ if not needed. 3) Launch Timing Analyzer 4) Run updated script from a menu ( Script > Run Tcl Script ) 5) End of the workaround if the script returns 0. 6) Add two constraints below to top sdc in your project such as ghrd_timing.sdc. set_net_delay -min 1.2 -from [get_registers {*|altera_gts_clock_gate:u_pcs_tx_clk_gated|en_flp}] -to [get_pins -compatibility_mode {*|u_pcs_tx_clk_gated|clk_gated|combout}] set_net_delay -min 1.2 -from [get_registers {*|altera_gts_clock_gate:u_pcs_rx_clk_gated|en_flp}] -to [get_pins -compatibility_mode {*|u_pcs_rx_clk_gated|clk_gated|combout}] 7) Recompile your design. 8) Go to 3 if a timing is met. This problem is currently scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition software.
Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why do I see cache coherency problems between the HPS and FPGA on HPS designs using ACE-Lite interfaces in Intel Quartus Prime Pro version 20.4 and earlier?
Description Due to a problem in the Intel© Quartus© Prime Pro software version 20.4 and earlier, incorrect AXI signal values may be seen on transactions between ARM® AMBA® AXI ACE-Lite Managers using the ARM AXI ACE-Lite protocol to connect to other logic in Platform designer, such as HPS FPGA to SOC Bridges or Avalon® Agents. This may be seen at run time as cache coherency errors. Resolution Patch 0.28 for the Intel® Quartus® Prime Pro software version 20.4 is available to fix this problem. Download and install the patch from the relevant link below, and re-compile your design. quartus-20.4-0.28-linux.run quartus-20.4-0.28-windows.exe quartus-20.4-0.28-readme.txt This problem is fixed in the Intel© Quartus© Prime Pro software version 21.1When does the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Altera® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?Error: Unknown option: -port_type while execute set_instance_assignment with the option
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and 25.1.1, you might see this error when running a "set_instance_assignment" with -port_type option e.g. Error:Unknown option: -port_type Error:--------------------------------------------------------------------------- Error:Usage: set_instance_assignment [-h] [-help] [-long_help] [-comment <comment>] [-disable] [-entity <entity_name>] [-fall] [-from <source>] -name <name> [-remove] [-rise] [-section_id <section id>] [-tag <data>] [-to <destination>] [<value>] Error: -h: Quick usage Error: -help: Short help Error: -long_help: Long help with examples and possible return values Error: -comment <comment>: Comment Error: -disable: Option to disable assignment Error: -entity <entity_name>: Entity to which to add assignment Error: -fall: Option applies to falling edge Error: -from <source>: Source of assignment Error: -name <name>: Assignment name Error: -remove: Option to remove assignment Error: -rise: Option applies to rising edge Error: -section_id <section id>: Section id Error: -tag <data>: Option to tag data to this assignment Error: -to <destination>: Destination of assignment Error: <value>: Assignment value Error:--------------------------------------------------------------------------- Error: while executing Error:"set_instance_assignment -name DUPLICATE_SYNC_FANIN …" Resolution A patch is available to fix this problem in the Quartus Prime Pro Edition Software version 25.3. Download and install patch 0.24 below. A patch is available to fix this problem in the Quartus Prime Pro Edition Software version 25.1.1. Download and install patch 1.49 below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Can I perform multiple compilations at the same time on one computer with a single-seat license?
Description You cannot perform multiple simultaneous compilations using the Quartus® Prime Software if you have a floating license with a single license seat. The number of concurrent compilations that can be run on a single computer cannot exceed the number of available license seats. If you have one fixed (node-locked) license, you can run multiple simultaneous compilations on that machine. Resolution See the related solution below for details on when the Quartus® Prime Software checks for available licenses. Related Articles When is a license checked out by the Quartus II software, IP cores and ModelSim-Altera Edition software?Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, you might see this error when compiling your design in Design Space Explorer II. Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space (Command was: lmap panel_name [::qed_lib::rdb_util::get_report_panel_names_matching -panel_name {} -string_match {Synthesis||Logic Synthesis Stage||Partition*||*Optimization Results||Multiplier Implementations||Multiplier Implementation Report} -regexp_match {}] {::qed_lib::rdb_util::get_report_panel_str -panel_name $panel_name})} Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.21 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why do I intermittently see reboot failure in the u-boot stage when running the Arria® 10 GSRD from GitHub?
Description While doing repetitive reboots, occasionally the subsequent reboot will fail, and it will be stuck in the u-boot stage and can't be recovered. Error Message : U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (1024 MiB). U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (1024 MiB). U-Boot SPL 2025.01-gcd3a9044d661-dirty (Mar 27 2025 - 08:49:19 +0000) Resolution Currently there is no workaround, users will need to power cycle the board to recover. Additional Information The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1. (QPDS25.3.1_REL_GSRD_PR).Why is no display output observed when using the VVP-Full Design Example version 24.2 in the Arria® 10 FPGAs?
Description Due to problems porting the Nios® II Processor design to the Nios® V Processor design in the Quartus® Prime Pro Edition Software version 24.2, the Arria® 10 FPGA VVP-Full Design Example does not work correctly; no output is displayed. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.