Error: CPU "intel_niosv_g_0" has no memories connected to its Avalon host(s)

Description

Due to a problem in the Quartus® Pro Edition software version 26.1.1, you might see an error when generating a Nios® V BSP, when the AXI Address Span Extender IP is inserted between the Nios V processor and the memory device connected to the instruction and data buses of the Nios V. This is because the AXI Address Span Extender IP does not recognize the connected device as a memory device for the Nios V processor.

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software version 26.1.1, follow these steps:

1. Open <QUARTUS_INSTALL_DIR>/ip/altera/merlin/axi_address_span_extender/axi_address_span_extender_hw.tcl

2. Go to around line 448, then delete the lines marked in red and add the lines marked in green as shown below.

# this assignment allows this component to appear as a memory target in the Nios II linker script configuration GUI  
# it makes the memory map of our slave look like a valid linker target memory region  
# <<to be revisited in 13.0>> 
- #set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1 
+ set_interface_assignment $slave embeddedsw.configuration.isMemoryDevice 1   

#  
# this assignment allows the macros of components attached to our master to appear in the Nios II system.h header  
# <<to be revisited in 13.0>> 
- #set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master" 
+ set_interface_assignment $slave embeddedsw.configuration.affectsTransactionsOnMasters $master

Please do not include the leading "+" and "-" characters.

3. Regenerate your design in Platform Designer.

Additional Information

This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. However, the updated statements are commented out by default. To apply the changes, remove the comment markers.