Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.
Why is no display output observed when using the VVP-Full Design Example version 24.2 in the Arria® 10 FPGAs?
Description Due to problems porting the Nios® II Processor design to the Nios® V Processor design in the Quartus® Prime Pro Edition Software version 24.2, the Arria® 10 FPGA VVP-Full Design Example does not work correctly; no output is displayed. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does Nios® V processor system simulation fail with no print-out message and multiple “x” values along the processor’s signals?
Description This problem may be seen in the Synopsys* VCS* and VCS* MX simulators when simulating the Nios® V processor system generated from Quartus® Prime Pro Edition Software version 23.1 to 23.4, or Quartus® Prime Standard Edition Software version 23.1std This is due to the X-propagation support in the simulators. Resolution To workaround this problem, follow these steps: Switch off the X-propagation feature on the processor core, Generate testbench system from the Platform Designer. Navigate into the Synopsys* simulator directory. $ cd <Project>/sys_tb/sys_tb/sim/synopsys Append -xprop=xpropconfig into the shell script in the vcs or vcsmx folder. For example: USER_DEFINED_ELAB_OPTIONS=”-xprop=xpropconfig” Create a file named xpropconfig in the vcs or vcsmx folder (beside the shell script). Copy the following text into xpropconfig, and change the processor entity name. tree {<Nios V processor HDL entity name>} {xpropOff}; Run the simulator. This problem is currently scheduled to be resolved in Quartus® Prime Pro Edition Software version 24.1 and later.Why is Agilex® 5 and Agilex® 3 FPGA External Memory Interfaces (EMIF) IP missing from the BSP Linker when the Nios® V processor Board Support Package is generated?
Description Due to a problem in the Quartus ® Prime Pro Edition starting since software version 24.1, the Agilex ® 5 and Agilex ® 3 FPGA EMIF IP is missing from the BSP Linker when generating the Board Support Package. This might occur for Nios ® V processor designs targeting Agilex 5 FPGA or Agilex 3 FPGA, that uses EMIF IP. This is because Agilex 5 and Agilex 3 FPGA EMIF IP are missing the isMemoryDevice agent information. Refer to Nios® V Processor Software Developer Handbook - Memory-Mapped Slave Information (PDF) for information about isMemoryDevice agent information. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 5 FPGAs and SoCs (PDF) for information Agilex ® 5 FPGA EMIF IP. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 3 FPGAs and SoCs (PDF) for information Agilex ® 3 FPGA EMIF IP. Resolution To work around this problem in the Quartus ® Prime Pro Edition in all the affected software version, apply either one of the following workarounds: Workaround 1: Manually add isMemoryDevice to the EMIF IP (in Platform Designer only) Select the s*_axi4 signal (mainband AXI4 from fabric to controller) that connects to the Nios ® V processor’s instruction/data manager. Right-click, and click Edit Component Instantiation ... Select s*axi4 and edit the Assignments. Enter new Key as embeddedsw.configuration.isMemoryDevice, and Value as 1. Save the new assignment. Generate a new BSP. Workaround 2: Manually define EMIF IP linker memory device Refer to the Nios V Embedded Processor Design Handbook - Defining Address Span Extender Linker Memory Device. The example demonstrates how to manually define Address Span Extender linker memory device. For this problem, apply the same procedure but on the EMIF IP directly. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software. Related Articles LPDDR4 not available in NIOS® V/g linker script - Agilex® 5 FPGA, Quartus® 26.1 Pro Issue with BSP Creation for Nios® V/m Using LPDDR4 on Agilex® 5 FPGA (Quartus® 24.1 & 24.3.1)Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Why is the eCPRI FPGA IP unable to run on hardware using Stratix® 10 E-Tile with the Nios® V Processor for FPGA and turn on the interworking function (IWF)?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2 in the example design, you may find that there is an error shown at the 10G transaction after changing the dynamic reconfiguration process from 25G to 10G. Resolution There is currently no plan to fix this behavior in a future Quartus® Prime release.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows* OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows* OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.Why does the Nios® V processor force Configuration Scheme with Memory Initialization for MAX® 10 FPGA?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and 24.1, you may see an error below when using Dual Compressed Image as the Internal Configuration mode for Nios® V Processor Design on MAX® 10 FPGA, Error (16031): The current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. Note: Assuming that memory initialization is disabled in every on-chip memory. Resolution To work around this problem, Download and install the patches below for the Quartus® Prime Standard Edition Software version 24.1. Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Windows (.exe) Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std (.txt) Download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1. Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Windows (.exe) Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std (.txt) The problem has been fixed starting with Quartus® Prime Standard Edition software version 25.1,Why does Nios® V/g processor experiences data corruption when it is enabled with TCM and ECC?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, data corruption might occur in Nios ® V/g processor designs with tightly coupled memory (TCM) and error correction code (ECC). Both features must be enabled to observe this problem. It is caused by an RTL bug in the processor, which renders failure when the processor executes sw (store word), followed by sh (store halfword) or sb (store byte) instructions. For example, # Initially, value of Y is 0x0001CCCC. li t0, 0x12345678 li t1, 0x200A sw t0, 0(Z) # Store 0x12345678 word into Z sh t1, 0(Y) # Store 0x200A into lower half of Y Result Final value of Y Description Expected 0x0001200A Upper-half of Y is preserved as 0x0001, while lower-half of Y is changed to 0x200A. Actual (Data Corruption) 0x1234200A Upper-half of Y is corrupted to 0x1234, while lower-half of Y is changed to 0x200A. The 0x1234 is from the previous Store Word (sw) instruction. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 26.1, apply either one of the solutions below: Disable TCM. Disable ECC. This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.Why does Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 turns compiler warnings into errors?
Description In the Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and later, you might see compilation error related to the following errors: Implicit int types (-Werror=implicit-int) Implicit function declarations (-Werror=implicit-function-declaration) Typos in function prototypes (-Werror=declaration-missing-parameter-type) Incorrect uses of the return statement (-Werror=return-mismatch) Using pointers as integers and vice versa (-Werror=int-conversion) Type checking on pointer types (-Werror=incompatible-pointer-types) This is due to an update in GCC 14 – GNU: Certain warnings are now errors, which affects future GCC versions. For more information, Ashling* RiscFree* IDE for Altera FPGAs software version 25.3.1 (1 st August 2025) is using GCC 13.2. Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is using GCC 15.2. Thus, Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and future versions are affected. Note that Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is paired with Quartus ® Prime Pro Edition software version 26.1. Resolution GNU recommends resolving all the new errors for better code quality. If necessary, you may refer to the workaround – GNU: Turning errors back into warnings. In Board Support Package Editor, add "-fpermissive" in hal.make.cflags_user_flags.
