Why is no display output observed when using the VVP-Full Design Example version 24.2 in the Arria® 10 FPGAs?

Description

Due to problems porting the Nios® II Processor design to the Nios® V Processor design in the Quartus® Prime Pro Edition Software version 24.2, the Arria® 10  FPGA VVP-Full Design Example does not work correctly; no output is displayed.

Resolution

To work around this problem, use the HDMI Arria® 10 Clocked Video design example or the Arria® 10 VVP-Full design example in the Quartus® Prime Pro Edition Software version 24.1.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.