Why does my design containing the Mailbox Client IP not compile after upgrading to Quartus® Prime Pro Edition software version 25.1?
Description Due to a problem with the Quartus® Prime Pro Edition software version 25.1, designs containing the Mailbox Client IP might fail during compilation after upgrading the IP. This problem affects designs targeting any Stratix® 10 FPGA or Agilex® FPGA device and containing both the Mailbox Client IP and the Advanced SEU Detection IP. If the Mailbox Client IP is upgraded but the Advanced SEU Detection IP has not been upgraded, you might see error messages during Analysis & Synthesis, such as: Error(13452): Verilog HDL Module Instantiation error at <filename>: module "altera_config_stream_endpoint_wrapper" has no parameter named "TYPE_NAME" Error(13452): Verilog HDL Module Instantiation error at <filename>: module "altera_config_stream_endpoint_wrapper" has no parameter named "INSTANCE_NAME" Resolution To avoid this problem, upgrade the Mailbox Client IP and the Advanced SEU Detection IP, even if the upgrade status is Recommended, not Required. A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 25.1. Download and install patch 0.01 from the following links: Quartus® Prime Pro Edition Design Software v25.1 Patch 0.01 for Windows (.exe) Quartus® Prime Pro Edition Design Software v25.1 Patch 0.01 for Linux (.run) Readme for Quartus® Prime Pro Edition Design Software v25.1 Patch 0.01 (.txt) The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why do the parsing results of a SOF file for Configuration via Protocol (CvP) created for Stratix® 10 FPGA or any of the Agilex® FPGA families indicate that the file is CvP disabled?
Description Due to a problem in Quartus® Prime Pro Edition Software version 24.3 and earlier, parsing SOF programming files using the method refered to in AN 955: Programmer's Configuration Debugger Tool will output a result which indicates that the SOF file generated from a project using Configuration via Protocol (CvP) is not enabled for CvP. This problem affects SOF files created for CvP targeting any Stratix® 10 FPGA or Agilex® FPGA family device. Resolution This issue does not affect functionality, and you can ignore this discrepancy. When you convert the SOF file to any other file programming format you plan to use CvP with, the parsing of the generated file will indicate that the file is enabled for CvP. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why is the Worst-Case MTBF not calculated for the nodes {*|soft_logics|rst_ctrl|pld_clk_ninit_done_sync_inst|din_s1}?
Description Due to a problem with the Quartus® Prime Pro Edition software version 25.1 and earlier, the "Worst-Case MTBF" is not calculated for the nodes {*|soft_logics|rst_ctrl|pld_clk_ninit_done_sync_inst|din_s1} and results in "n/a (no valid slack)" by Timing Analyzer. This problem affects all designs containing the P-Tile PCIe FPGA IP. Resolution A patch is available to fix this problem in the Quartus® Prime Pro Edition software version 25.1. Download and install patch 0.06 from the following links: Download patch 0.06 for Windows (quartus-25.1-0.06-windows.exe) Download patch 0.06 for Linux (quartus-25.1-0.06-linux.run) Download the Readme for patch 0.06 (quartus-25.1-0.06-readme.txt) A patch is available to fix this problem in the Quartus® Prime Pro Edition software version 24.3.1. Download and install patch 1.21 from the following links: Download patch 1.21 for Windows (quartus-24.3.1-1.21-windows.exe) Download patch 1.21 for Linux (quartus-24.3.1-1.21-linux.run) Download the Readme for patch 1.21 (quartus-24.3.1-1.21-readme.txt) The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.
Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps.Can the Multi-Channel DMA for PCI Express* IP Design Example (P-tile Avalon® Memory-Mapped Interface DMA variant) be simulated using Questa*-Altera® FPGA Edition or Mentor Graphics* ModelSim?
Description No, the Multi-Channel DMA for PCI Express* IP (P-tile AVMM DMA variant) Design Example is not currently supported for simulation on Questa*-Altera® FPGA Edition or Mentor Graphics* ModelSim*. Synopsys* VCS* is currently the only supported simulator for this IP variant. Resolution The Multi-Channel DMA for PCI Express IP Design Example User Guide (HTML) has been updated to reflect the supported simulators.Why does the P-Tile Avalon® Streaming IP for PCI Express* show an RDC-50001 warning?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.3 and later, you might see the following violation for the P-tile Avalon® Streaming IP for PCI Express* RDC-50001 - Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain Resolution Waive warning, copy da_drc.dawf file from the P-tile Avalon® Streaming IP for PCI Express* PIO example design and add it to the project's folder and recompile.Why does the R-tile AXI Streaming IP for PCI Express* fail compilation in the Quartus® Prime Pro Edition software version 25.1?
Description Due to a problem in the 25.1 version of the R-tile AXI Streaming IP for PCI Express*, compilation will fail during the fitter stage when pin locations are assigned with the following or similar error(s): Error(171016): Can't place node "hip_serial_tx_n_out0~pad" -- illegal location assignment Resolution To work around this problem, remove all the location assignments for the AXI Streaming IP for PCI Express* in the Assignment Editor or by editing the project .QSF file, and recompile the design. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does the FPGA Power and Thermal Calculator (PTC) and Quartus® Power Analyzer (QPA) underestimates/overestimates the static power consumption of the HBM resources?
Description Due to a problem in FPGA Power and Thermal Calculator and Quartus® Power Analyzer (QPA) version 23.4 and prior in the below use cases, the static power estimation for HBM resources might not be accurate. Power Supplies affected by these issues are VCCIO_UIB* and VCCM_PUMP_HBM_* If the type of HBM used is 16GB Number Of Used HBMs Inaccuracy 0 PTC Underestimates By ~ 0.5 W 1 PTC Underestimates By ~ 0.5 W 2 PTC Overestimates By ~ 0.5 W If type of HBM used is 32GB Number Of Used HBMs Inaccuracy 0 PTC Underestimates By ~ 1.05 W | QPA underestimates by ~0.5 1 PTC Underestimates By ~ 1.05 W | QPA underestimates by ~0.3 2 0 Resolution This issue has been fixed in the FPGA Power and Thermal Calculator version 24.1.Why does the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example simulation fail when using the Questa*-Altera® FPGA Edition Software?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and later, simulation of the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE mode enabled will fail when using the Questa*-Altera® FPGA Edition Software. Refer to the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example User Guide Version Found: 25.1 Resolution To work around this issue, do one of the following: Generate the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE Mode Disabled when simulating with the Questa*-Altera® FPGA Edition Software or, Use full version of the Questasim* Software to simulate the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE Mode enabled. A patch is NOT available to fix this issue.Why does the Power Thermal Analyzer tool display device family compatibility errors when opening files from different device families in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3, during a single session, if a new Power Thermal Analyzer (PTA) design file is created targeting a specific device family, all subsequent PTA design files opened will be loaded targeting the same device family. This occurs regardless of the actual target device defined in those files. This problem occurs when switching between Stratix® 10 FPGA and Agilex® FPGA device families within the same session. For example, if you first create a PTA file for a Stratix™ 10 FPGA device and then open a PTA file meant for an Agilex® 7 FPGA device, the Agilex® 7 FPGA file will incorrectly be loaded as targeting the Stratix® 10 FPGA device. This results in the error: "Error (25383): The Stratix® 10 FPGA PTA does not currently support opening files created by the Agilex® 7 FPGA PTA. Import canceled." The same issue occurs in reverse when opening Stratix® 10 FPGA PTA files after creating an Agilex® FPGA PTA file. Resolution You can avoid this issue using one of the following methods: Close and reopen Quartus® Prime Pro Edition Software before opening PTA files from different device families. This method works when PTA is launched from Quartus® Prime Pro Edition Software; for standalone PTA, closing and reopening PTA before opening different device family files is more appropriate. Create a new PTA file using the target device family, then open the desired file from the recently created PTA file. Use the open_design_file Tcl command by copying the equivalent Tcl command displayed in the Tcl Console and modifying it to replace the target device family in the -family parameter to match the desired device family. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.