Why does Nios® V/g experience data corruption when using DTCM?
Description Due to a problem in Quartus® Prime software, data corruption may occur when running a Nios® V/g processor application that interacts with a Tightly-Coupled Memory (TCM). This happens because of a RTL bug in the load-store unit. This problem is affecting Nios® V/g processor in, Quartus® Prime Pro Edition release 25.3.1 and earlier Quartus® Prime Standard Edition release 25.1 and earlier When Nios® V/g processor executes a non-TCM load (i.e. Load from On-Chip Memory or memory-mapped CSR) followed by a Data TCM load, the latter corrupts the former. This causes the non-TCM load to receive incorrect load data. For example, lw rd1,0(non-TCM) lw rd2,0(TCM) Expectation Actual Failure rd1 = load data from address “non-TCM” rd1 = load data from address “TCM” rd2 = load data from address “TCM“ rd2 = load data from address “TCM“ Resolution This problem is fixed in Quartus® Prime Pro Edition 26.1 and is scheduled to be resolved in a future Quartus® Prime Standard Edition release. Additional Information A patch is available to fix this problem. Quartus® Prime Standard Edition Software v25.1 Patch 0.01 Please contact Altera Support for additional support.Can the F-Tile FGT PMA lane in neutral state of Dynamic Reconfiguration be preserved?
Description Yes, the F-Tile FGT PMA lane can be preserved even after moving to neutral state from normal state by Dynamic Reconfiguration. Resolution While the F-Tile FGT PMA lanes are in the neutral state, users need to keep the TX PMA and RX PMA of the unused lanes in reset until those lanes are reactivated and placed back into operating mode in the future. The performance of those lanes will not be degraded after they are reactivated.Why does the Quartus® Prime Pro Edition Software report that no IOPLL is available when placing the Low Latency E-Tile 40G Ethernet FPGA IP in an HPS shared GPIO Bank?
Description Due to a clocking limitation of HPS Shared GPIO Bank, the Low Latency E-Tile 40G Ethernet FPGA IP cannot be placed in an HPS Shared GPIO Bank when a design targets Agilex® 7 FPGA F-Series. If the IP placement requires its IOPLLs to use an HPS Shared GPIO Bank, the fitter may report that no IOPLL IP is available and compilation may fail during the fitter stage. The Low Latency E-Tile 40G Ethernet FPGA IP uses IOPLL IPs configured in Normal Compensation mode. However, the IOPLL resources in an HPS Shared GPIO Bank support Direct Compensation mode only. Consequently, the fitter cannot legally place the IOPLLs in the Low Latency E-tile 40G Ethernet FPGA IP in an HPS Shared GPIO Bank. Resolution To avoid this problem, place the Low Latency E-Tile 40G Ethernet FPGA IP in a supported non-HPS Shared GPIO Bank.Why does the dynamic reconfiguration simulation of Phylite IP design fail in the Questa* – Altera® FPGA Edition ?
Description Due to a problem in the External Memory Interfaces (EMIF) IP, simulation running in the Questa* – Altera® FPGA Edition might fail when you set the use dynamic reconfiguration on Agilex® 7M R0 devices. Resolution To work around this problem, change the device selection to a non-R0 OPN during simulation.Design Assistant CDC-50001, CDC-50011, and CDC-50012 warnings from the F-Tile Dynamic Reconfiguration one-hot profile select paths
Description When compiling designs that use the F-Tile Dynamic Reconfiguration Suite IP, Design Assistant may report CDC-50001, CDC-50011, or CDC-50012 warnings whose source list includes the DR one-hot profile select (dr_ctrl_sip_inst\|dr_profile_1hot_sel_src_sync\|sync[*] or equivalent one_hot_sel_int[*]). CDC-50001 occurs when the one-hot profile select drives generated tile-adapt mux logic. CDC-50011 occurs when synchronized one-hot bits pass through generated profile-selection OR/mux gating with PHY ready or reset_ack level status before an existing destination synchronizer; two aggregate TX paths may also include a level-status reduction AND before that synchronizer. CDC-50012 occurs when the quasi-static one-hot select is added to a cone that also contains a status signal from another source clock, causing Design Assistant to classify the destination synchronizer as driven by multiple domains. It’s safe to ignore these warning. All the three warnings are expected Design Assistant noise, not functional issues. The one-hot selection changes only during the controlled DR sequence, remains stable during normal operation, and the associated status signals are synchronized level signals rather than pulses. Resolution To work around this problem, you can waive these paths in the Design Assistant. There is no plan to fix this problem in the future. It’s safe to ignore these warnings.Does the TOD_MASTER_156_25MHz_P signal on the Agilex® 7 FPGA M-Series require external bias circuitry when AC-coupled?
Description The Agilex® 7 FPGA M-Series 039 production-board design uses the TOD_MASTER_156_25MHz_P signal with AC coupling. There is no information whether this AC-coupled interface requires additional external bias circuitry for correct signal transmission and operation. Resolution The reference implementation shows TOD_MASTER_156_25MHz_P with AC coupling and with external bias circuitry. Follow the implementation shown in the AN 555: True Differential Signaling Termination and Biasing for Agilex® 7 FPGA M-Series, Agilex® 5 FPGAs, and Agilex® 3 FPGAsWhy does the Agilex® 7 FPGA M-Series Development Kit fail configuration with bitstream error 0x0015?
Description When configuring an SOF file on the Agilex® 7 FPGA M-Series Development Kit, the configuration process fails and reports bitstream error subcode 0x0015. Resolution Use Quartus® Programmer version 25.3 or later to program the device. Configuration completes successfully when using Quartus® 25.3, and no special processing or modifications to the generated SOF file are required.Why does the Quartus® Prime Programmer GUI fail JIC programming with "Different TAPS selected" or "Operation failed" in AS mode for device AGIB027R31B1E1VAA?
Description In Quartus® Prime Software versions 24.2 and 25.1, the Quartus Programmer GUI may fail during JIC programming when the board is in Active Serial (AS) boot mode. This issue is specific to the Agilex® 7 SoC device with OPN AGIB027R31B1E1VAA paired with QSPI flash MT25QU01GBBB8E12-0SIT. The GUI reports "Different TAPS selected." or "Operation failed" when the flash already contains existing data. The same JIC programs successfully on the same board using the quartus_pgm command-line tool. Note: This issue does not affect all Agilex®7 FPGA OPNs - it has been reproduced only on AGIB027R31B1E1VAA. Resolution This issue is specific to OPN AGIB027R31B1E1VAA on Quartus Prime versions 24.2 and 25.1. To resolve or work around this issue: Upgrade to Quartus® Prime Software version 25.1.1 or later, where this issue is resolved for AGIB027R31B1E1VAA. Alternatively, use the quartus_pgm command-line utility to program the JIC file instead of the GUI Programmer on affected versions (24.2 and 25.1).Why isn't the Debug Toolkit using AXI Streaming IP for PCIe* with F-Tile variant shown in the System Console window when using the Quartus® Prime Pro Edition software version 25.3 and 25.3.1 ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and 25.3.1, the Debug Toolkit using AXI Streaming IP for PCIe* with F-Tile variant isn't shown in the System Console window. Resolution A patch is available to fix this problem for the Quartus Prime Pro Edition software versions 25.3. Download and install patch 0.37 below. This problem is fixed beginning with the Quartus Prime Pro Edition software version 26.1.Why are setup timing violations reported on the F-Tile Support Logic and Direct PHY paths?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe setup timing violations on clocks associated with F-Tile support logic and Direct PHY paths. The failing path was between Soft Reset Controller (SRC) and Direct PHY (DPHY) logic due to synchronizer problem. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
