Internal Error: Sub-system: QCU, File: /quartus/comp/qcu/qcu_qis_utility.cpp, Line: 1673
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 or earlier, you might see this internal error when you run Start Standard to Pro Lint. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.1.1, download and install the patch below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Why does the Synchronous FIFO Parameterizable Macro (sync_fifo) incorrectly output all zeroes data after being empty?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 or earlier, you might see that the first output data from the FIFO after the FIFO has been empty is incorrectly set to zero. This problem occurs when using the Synchronous FIFO Parameterizable Macro (sync_fifo) in show-ahead mode. Resolution To work around this problem, instantiate the FIFO FPGA IP instead of the Synchronous FIFO Parameterizable Macro. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
Why is receiver termination reported as “Off” for the PCI Express* differential data pair in the Quartus® Prime Pro Edition software version 25.1.1 for design targeting Agilex™ 7 FPGA F-Tiles Devices?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.1.1 and earlier, the on-chip termination setting for the PCIe* differential data pair incorrectly reported in Fitter Report. However, the actual default receiver termination was set to 100 Ohms. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1. The default receiver termination is updated to 85 Ohms. The existing 100 Ohms continues to be available as an option after the fix. Both 85 Ohms and 100 Ohms receiver termination settings have been validated, and test results confirm compliance with PCIe specifications. The receiver on-chip termination parameter will be available in the IP Parameter Editor for F-Tile Avalon Streaming IP for PCI Express after the fix. The 100 ohms setting in the existing design will be retained when migrating to the new Quartus Prime Pro Edition software version, unless the user explicitly changes it in the IP Parameter Editor. Existing designs can continue using the 100 ohms setting without problem, while the 85 ohms setting is recommended for new designs. In the Quartus® Prime Pro software Compilation Report, the receiver termination setting can be verified under: Synthesis > Analysis & Elaboration Stage > Parameter Settings by Entity Instance > Parameter Settings for User Entity ftileb_ag_v0 Instance: pcie_ed_auto_tiles. Parameter Name: *rx_onchip_termination Value: *rx_onchip_termination_r_1 (representing 85 ohms) *rx_onchip_termination_r_2 (representing 100 ohms)Internal Error: Sub-system: QPR, File: /quartus/comp/qpr/qpr_route_mask_generator_details.h, Line: 594
Description Due to a problem in Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, you might see this internal error at the fitter stage when compiling a Partial Reconfiguration (PR) implementation that uses a global reset on fast input/output registers. The base revision compiles successfully, the error occurs only in PR implementations with this global reset usage. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v25.1.1 or v25.1, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2 and later, the Multi-Channel DMA FPGA IP for PCI Express* may stall or cease operation when the Q_SIZE parameter is set to 0x10. Resolution The recommended workaround is to limit Q_SIZE to 0xF. If your design requires a Q_SIZE of 0x10, upgrade to the Quartus® Prime Pro Edition software version 25.3.1, regenerate the Multi-Channel DMA FPGA IP for PCI Express, and recompile the design to ensure the fix takes effect.Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Is my Development Cable affected by this? If your USB Blaster III Development cable has a serial number ranging from UB3000000 - UB3006090, then you will need to update the PID. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Why does Agilex® 7 FPGA M-Series fail to be reconfigured after applying a software cold reset from U-Boot proper in Quartus® Prime Pro release 26.1?
Description Due to an incorrect implementation of the cold reset flow in U-Boot proper, in Agilex® 7 FPGA M-Series in release 26.1, the FPGA/JTAG is not kept in a clean idle state, resulting in the JTAG reconfiguration rejection. This causes the following error observed when you try to reconfigure the device after the cold reset: SOCFPGA_AGILEX7M # reset resetting ... Mailbox: Issuing mailbox cmd REBOOT_HPS rolando@rolando3-linux-lab:~/tasks/testbin$ quartus_pgm -c 1 -m jtag -o "p;ghrd.hps.rbf@2" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 26.1.0 Build 110 03/26/2026 SC Pro Edition Info: Copyright (C) 2026 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Tue Jun 30 18:42:30 2026 Info: System process ID: 93542 Info: Command: quartus_pgm -c 1 -m jtag -o p;ghrd.hps.rbf@2 Info (213046): Using programming cable "Intel Agilex M-Series Development Kit - HBM2e Edition on AN04WVAW035PS.an.altera.com [1-12]" Info (213011): Using programming file ghrd.hps.rbf with checksum 0xA66FE7E5 for device AGMF039R47AC@2 Info (209060): Started Programmer operation at Tue Jun 30 18:42:32 2026 Info (18942): Configuring device index 2 Error (18952): Error status: Device does not accept configuration request Error (18939): Unexpected error in JTAG server: JTAG chain broken Error (18952): Error status: Detected error when rescan jtag chain Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue Jun 30 18:42:43 2026 Error: Quartus Prime Programmer was unsuccessful. 4 errors, 0 warnings Error: Peak virtual memory: 1235 megabytes Error: Processing ended: Tue Jun 30 18:42:43 2026 Error: Elapsed time: 00:00:13 Error: System process ID: 93542 Resolution To work around this problem, you can disable the watchdog timer before issuing the cold reset. This can be done using the wdt stop command from the U-Boot shell as shown next: SOCFPGA_AGILEX7M # wdt list watchdog@ffd00200 (designware_wdt) SOCFPGA_AGILEX7M # wdt dev watchdog@ffd00200 SOCFPGA_AGILEX7M # wdt stop SOCFPGA_AGILEX7M # reset Note: You need to build your U-Boot to support the wdt command by setting CONFIG_CMD_WDT=y in your build configuration. You can also apply the cold reset from Linux, in which the error is not observed. For this, you can use the reboot command from the Linux shell. This problem will be fixed in a future release.Why does the Simulation Library Compiler fail due to a missing km_220model.sv file in Quartus® Prime Pro Edition 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, the Simulation Library Compiler might fail when compiling simulation libraries for a supported third-party simulator (for example Aldec Riviera-PRO*, Siemens EDA QuestaSim*, or Cadence Xcelium*) if you compile libraries using RTL-only or Compatible Mode for Quartus simulation flow without selecting a specific device family. The compile might stop with an error that a simulation source file such as km_220model.sv cannot be found under the Quartus installation quartus/eda/sim_lib directory. Example errors: Cannot find source file: <Quartus installation>/quartus/eda/sim_lib/km_220model.sv Failed to open design unit file km_220model.sv in read mode. This occurs because the Simulation Library Compiler requests certain simulation model files that are not included in the Quartus® Prime Pro Edition software version 26.1 installer. Those model files are not required to simulate designs that target currently supported device families. Libraries that already compiled successfully before the error remain valid. Refer to the Quartus Prime Pro Edition User Guide: Third-party Simulation (document ID: 683870). Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 26.1, follow these steps: Open a command prompt or terminal where the Quartus Prime software and your simulator license are available. Re-run the Simulation Library Compiler and specify your target device family with the -family option. Do not use an RTL-only compile that omits -family when you only need libraries for one device family. Example (Aldec Riviera-PRO, Verilog, Quartus-compatible mode): quartus_sh --simlib_comp -tool rivierapro -language verilog -mode quartus -family "Arria 10" -tool_path <path_to_riviera_bin> -directory <output_directory> Replace Arria® 10 FPGA with your device family name. Run quartus_sh --help=simlib_comp to list valid -family values for your install. Alternatively, in the Quartus Prime software GUI: Click Tools > Launch Simulation Library Compiler. Select your simulation tool, HDL language, target device family, and output location. Start Compilation. If you must keep an RTL-only or all-library compile on version 26.1 only: Create an empty placeholder file named km_220model.sv in <Quartus installation>/quartus/eda/sim_lib/. Re-run the Simulation Library Compiler. If the compile reports another missing file under sim_lib with a similar name pattern, create an empty placeholder for that file and continue. This problem is fixed in the Quartus® Prime Pro Edition Software version 26.3.
