Why does the EMIF Debug Toolkit report fixed channel 1 driver margin values for two channel memory designs?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1 and earlier, EMIF Debug Toolkit might report the same fixed driver margin values for every DQ pin of channel 1 when used with 2chx16 memory designs targeting Agilex® 3, Agilex® 5, and Agilex® 7 FPGA M-Series devices. The same behavior might also occur during Vref margining.

Resolution

Only the displayed values are affected. It does not impact the functionality of the hardware interface.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.