Why do Quartus® Prime Pro 26.3 and earlier fail to build a Agilex® 5/Agilex® 3/Agilex® 7 FPGA M-Series VDS based design whose RTL has been generated with VDS?
Description Due to a problem related to how VDS handles the EMIF IO96B IP (emif_io96b_hps.ip) during the RTL generation, the Quartus PRO 26.3 and earlier compilation of a Agilex® 5/Agilex® 3/Agilex® 7 FPGA M-Series design fails at Synthesis stage, when RTL is generated using VDS, with the following error: Error(16045): Instance "u_baseline_top|u_shell_subsys|u_hps_subsys|u_emif_hps|emif_io96b_hps_inst" instantiates undefined entity "emif_io96b_hps_emif_io96b_hps_510_prw4fva" : Error: Failed to elaborate design: Error: Flow failed: Errors generated during elaboration Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 1 warning Error: Peak virtual memory: 2354 megabytes Error: Processing ended: Mon Oct 12 13:24:09 2026 Error: Elapsed time: 00:00:27 Error: System process ID: 2357227 Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning Resolution To workaround this problem, don’t use VDS to generate the RTL. If you need to modify or edit the design in VDS, save the updates and leave VDS without generating the RTL. Go back to Quartus, in the Compilation Dashboard > Compilation Flow window open the Open Settings Dialog in the IP generation section, go to Board and IP settings and in the IP regeneration policy section, select Always regenerate design files for IP cores; press Apply button and OK button. Proceed with the full design compilation. The same can be done if you add the following setting into the corresponding .qsf file: set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP This problem will be fixed in a future release.Why does the Quartus® Prime Pro Edition Software version 26.1 complete compilation even when two PCIe* Hard IPs are enabled for CvP application?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 and earlier, compilation may complete successfully when more than one PCIe* IP is enabled for CvP application, which conflicts with the description in the Configuration via Protocol (CvP) Implementation User Guide. Resolution Currently, there is no workaround. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Quartus® Prime Pro Edition Software version 26.1 complete compilation even when two PCIe* Hard IPs are enabled for CvP application?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 and earlier, compilation may complete successfully when more than one PCIe* IP is enabled for CvP application, which conflicts with the description in the Configuration via Protocol (CvP) Implementation User Guide. Resolution Currently, there is no workaround. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does compilation fail after restoring a project archive?
Description Due to a problem in the Quartus® Prime Pro Edition software Windows version 26.1.1, an archived project that compiles successfully before may fail to compile after it is restored from a Quartus Archive File (.qar). Some IP-generated files may be missing from the restored project. Resolution To work around this problem, open your project from the QAR file and change the following IP Generation settings: Open Assignments → Settings → IP Generation. Select VHDL as the IP generation language. Note: Do not regenerate the IP.Why do Remote System Update (RSU) use cases fail in Agilex® 3 FPGA device in QPDS26.1.1_REL_GSRD_PR release?
Description Due to a problem in QPDS26.1.1_REL_GSRD_PR release, most of the Remote System Update (RSU) use cases are not functional in Agilex® 3 FPGA, when these are exercised from U-Boot. One of the issues observed is the scenario in which the rsu update command is called to load an application from a valid slot address; the error is shown next: SOCFPGA # rsu update 0x00600000 RSU: RSU update to 0x0000000000600000 RSU: mbox_rsu_update failed (1023) On Linux, most RSU functionality works correctly, but the rsu_client --log command reports an incorrect STATE after a WDT expiration event. ./rsu_client --log VERSION: 0x0ACF0202 STATE: 0xF0060001 ← Linux should report 0xf0060002. The 0xF0060001 value is normally reported by U-Boot. CURRENT IMAGE: 0x0000000000800000 FAIL IMAGE: 0x0000000000800000 ERROR LOC: 0x00000000 ERROR DETAILS: 0x00000000 RETRY COUNTER: 0x00000001 Resolution To workaround for this problem you can use the Quartus design (.sof) from QPDS26.1_REL_GSRD_PR release. You can also use all the components (.sof, hps software and DCMF ) from QPDS26.1_REL_GSRD_PR release. This problem will be fixed in a future release.Why does Linux* fail to access components from the QSPI in any device in QPDS26.1.1_REL_GSRD_PR release and onwards?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, atomic compare-and-swap operations on the CXL.cache AXI interface might fail to swap the expected value when AWBURST is set to 2 (WRAP) for designs targeting Agilex® 7 FPGAs and SoCs with R-Tile CXL Type 2 IP. This behavior can occur for 1-, 2-, 4-, and 8-byte compare-and-swap operations that follow the attribute settings in the Agilex 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP User Guide, Table 9. Attribute Settings for Different Data Block Sizes. Compare-and-swap operations with AWBURST set to 1 for aligned addresses complete successfully for the same data sizes. Associated Quartus Suite bug: QS-22385. Resolution To work around this problem in the Quartus® Prime Pro Edition Software, install patch 0.13 for Quartus® Prime Pro Edition Software version 26.1, then regenerate or rebuild the R-Tile CXL IP design and revalidate the CXL.cache atomic compare-and-swap WRAP sequence. A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 26.1. Download and install patch 0.13 below. This problem is scheduled to be resolved in the Quartus® Prime Pro Edition Software version 26.1.1.Why does Linux fail to access QSPI flash components across all supported devices in the QPDS26.1.1_REL_GSRD_PR release?
Description Due to the change in the default value (from ‘n' to 'y’) of the CONFIG_MTD_SPI_NOR_USE_4K_SECTORS config in Linux from QPDS26.1.1_REL_GSRD_PR release and onwards, Linux may fail to access components from the QSPI flash device if the component was built with a configuration using an erase sector size of 64KB. This may be the case for loading the Linux file system (with jffs or ubi format), which is normally built for a QSPI erase sector size of 64 KB in Altera binary build recipes. This problem may be observed in any of the Altera SoC devices. Resolution To work around this problem, you need to change the value of the CONFIG_MTD_SPI_NOR_USE_4K_SECTORS config to 'n'. You can do this by adding this line to the arch/arm64/configs/defconfig file: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n You can also override the value of this config as shown next: git clone -b QPDS26.1.1_REL_GSRD_PR GitHub - altera-fpga/linux-socfpga: Linux development repository for socfpga cd linux-socfpga cat << EOF > config-fragment-agilex5 CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n EOF make defconfig ./scripts/kconfig/merge_config.sh -O ./ ./.config ./config-fragment-agilex5 <continue here the regular Linux build> It is not expected that this problem will be fixed in a future release, as the community rejected changing the CONFIG_MTD_SPI_NOR_USE_4K_SECTORS config to 'n'.Why is data transfer performance low when using the HPS DMA Controller?
Description Due to the design of the Hard Processor System (HPS) Direct Memory Access Controller (DMAC) in Altera FPGA Agilex® 7, Agilex® 5, and Agilex® 3 devices, data transfer throughput across the HPS-to-FPGA (H2F) and Lightweight HPS-to-FPGA (LWH2F) bridges can appear low-sometimes as low as approximately half of the theoretical maximum-when you use the HPS DMAC for transfers via the H2F or LWH2F path. The generic DMA controller in the HPS is optimized and sized for peripheral data movement within the HPS complex and may not move data near the maximum theoretical throughput across the H2F or LWH2F bridges. Resolution To work around this limitation when higher throughput is required between the HPS and FPGA fabric, follow these steps: Evaluate a fabric-based DMA controller for data transfers between the HPS and FPGA fabric. Measure the resulting throughput against your application bandwidth requirements to determine whether the fabric-based DMA meets your needs. This behavior reflects HPS DMAC sizing for bridge traffic; it is not scheduled to be changed in a Quartus® Prime software release.
Does Altera provide 3D mechanical models for device packages?
Description 3D Package Step (STP) models are available for Agilex® FPGA devices. They are included in the Compact Thermal Models that are available to customers with “My Collateral” secure content entitlement. Resolution To request “My Collateral” entitlement, visit your My Altera dashboard and request “My Collateral” access. A on-line Non-disclosure agreement is required.Why I can't change the device family in Power and Thermal Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you may not be able to change to a different device family in Power and Thermal Analyzer (PTA) after you create or open a design. For example, if you open a design targeting a Stratix® 10 device, you may not be able to change to an Agilex® FPGA device. In version 26.1, if you select File > New File to create a new PTA design, the new file wizard does not appear. Without the wizard, you cannot select a different device family when creating a new file. Resolution PTA locks a design to the device family selected when the file is created. To explore power consumption across different device families, create a new PTA file in the target family and import your existing design. To import an existing PTA design into a different device family: Create a new PTA file targeting the desired device family. Use the Import function to bring your existing PTA design into the new file. If you chose the wrong device family when creating a file, close the existing file and create a new one. In the File menu, select New File, and select the correct device family in the new file wizard. In version 26.1 of Power and Thermal Analyzer, the new file wizard does not appear when you select New File. To work around this issue, exit and restart PTA. After restarting, select File > New File to open the new file wizard and select the correct device family.
