Why does Linux* fail to access components from the QSPI in any device in QPDS26.1.1_REL_GSRD_PR release and onwards?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, atomic compare-and-swap operations on the CXL.cache AXI interface might fail to swap the expected value when AWBURST is set to 2 (WRAP) for designs targeting Agilex® 7 FPGAs and SoCs with R-Tile CXL Type 2 IP.

This behavior can occur for 1-, 2-, 4-, and 8-byte compare-and-swap operations that follow the attribute settings in the Agilex 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP User Guide, Table 9. Attribute Settings for Different Data Block Sizes. Compare-and-swap operations with AWBURST set to 1 for aligned addresses complete successfully for the same data sizes.

Associated Quartus Suite bug: QS-22385.

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software, install patch 0.13 for Quartus® Prime Pro Edition Software version 26.1, then regenerate or rebuild the R-Tile CXL IP design and revalidate the CXL.cache atomic compare-and-swap WRAP sequence.

A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 26.1. Download and install patch 0.13 below.

This problem is scheduled to be resolved in the Quartus® Prime Pro Edition Software version 26.1.1.