Why do I see a simulation failure with the F-Tile Multi Channel DMA IP for PCI Express* Design Example using the Quartus® Prime Pro Edition Software version 26.1 ?
Description Due to a problem in the Quartus Prime Pro Edition Software version 26.1, you may encounter simulation errors with the F-Tile Multi Channel DMA IP for PCI Express* Design Example. Synopsys VCS/VCS-MX: Error-[SE] Syntax error Following verilog source has syntax error : "./../..//pcie_ed_sim_tb.v", 2015: token is ')'... Error-[TMENF-IL] Top Module/Entity not found Top module/entity/config "pcie_ed_sim_tb.pcie_ed_sim_tb" is not found in library "PCIE_ED_SIM_TB". Error-[NM] No modules defined No modules defined in current design file(s). Siemens Questasim: ** Error: /mentor/questasim/2025.3/linux64/linux_x86_64/qrun failed. Error in macro ./run_msim_setup.tcl line 52 Cadence Xcelium: xmelab: *E,NOUNIT: Unable to find a unit named 'pcie_ed_sim_tb.pcie_ed_sim_tb' in the libraries. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_sim_tb.pcie_ed_sim_tb' does not exist in the libraries. Aldec Riviera-Pro: Error: VCP2000 .../pcie_ed_sim_tb/pcie_ed_sim_tb/sim/pcie_ed_sim_tb.v : (1951, 6): Syntax error. Unexpected token: ). This problem is attributed to a limitation in the provided simulation testbench within this software release. It is important to note that this behavior is confined to the simulation environment and does not impact the functionality or performance of the design on hardware. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer?
Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why am I observing .sof generation failure when selecting VSR_MODE_HIGH_LOSS in F-Tile JESD204B IP Design Examples?
Description The VSR_MODE_HIGH_LOSS option is available in the dropdown menu of the IP GUI for F-Tile JESD204B IP Design Examples. However, starting from Quartus® Prime Pro Edition Design Software version 25.3, this option is deprecated and no longer supported. With the updated F-Tile firmware starting in Quartus® Prime Pro Edition Design Software version 25.3, VSR_MODE_HIGH_LOSS and VSR_MODE_LOW_LOSS are treated equivalently. As a result, selecting VSR_MODE_HIGH_LOSS for hardware testing (e.g., on a development kit) allows the Design Example to compile successfully, but the SOF generation fails. Resolution Users should select VSR_MODE_LOW_LOSS. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.Why Does the Simplex RX/TX Design Example Fail During HSSI Support Logic Generation with a QHIP_IP_PROPERTY Case Sensitivity Error in F-Tile JESD204B IP?
Description Due to a problem in Quartus® Prime Pro Edition Design Software Version 25.3, the F-Tile JESD204B IP Simplex RX/TX example design may fail with the following error in compilation: "Cannot find QHIP_IP_PROPERTY tile_ip_sip_instances with value …..." Resolution To work around this compilation error, manually remove the QHIP_IP_PROPERTY assignment from the .qip file in the Design Example folder. Steps: Navigate to the following path in the Design Example directory: intel_jesd204b_gts_<data path>/example_design/ed_synth/ip/jesd_gts_ss<data path>/jesd_gts_ss_<data path>intel_jesd<data path>/ Open the QIP file: jesd_gts_ss_<data path>intel_jesd<data path>.qip Locate and remove the line containing the QHIP_IP_PROPERTY assignment. Save the file and retry the compilation. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.Why the Error Injection using Linux* debugfs interface does not work for SDMMC ECC Port B?
Description Due to a problem in the EDAC (Error Detection and Correction) driver, the Error Injection using Linux* debugfs interface on SDMMC ECC Port B is not functioning. The error injection command below does not write to INIT test register as intended. echo C > /sys/kernel/debug/edac/sdmmca-ecc/altr_trigger As comparison, when writing directly to the INITTEST register, single bit error interrupt is shown to be working. root@agilex7dksiagf014eb:~# devmem2 0xFF8C8C26 h 0x1 ----- /dev/mem opened.[ 1785.685802] EDAC DEVICE6: CE: Altera ECC Manager instance: sdmmcb-ecc0 block: sdmmcb-ecc0 count: 1 'sdmmcb-ecc' This issue is impacting Agilex® 7 SoC FPGA devices and Quartus® Prime software of version 25.3.1 and older. Resolution To workaround this issue, apply the patch by following the instructions below: git clone the repo https://github.com/altera-fpga/linux-socfpga/commits/socfpga-6.18.2-lts/ run: git format-patch-1 Make sure the commit is included in the patch: https://github.com/altera-fpga/linux-socfpga/commit/be94a41dfaf7e124a5547ac8948b36f097a73c90 Use “git am” to apply the patch onto your source code. Additional Information This issue is fixed in Quartus Prime software version 26.1 onwards.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1?
Description The latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1 can be downloaded from the following links. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 1.33fw: Fixed race condition in handling SHA isr and resumption of FPGA data blocks.Drain DMA post a configuration/PR to flush out left over data if any. Firmware version 1.22fw: Enabled 85 Ohm Rx Termination for PCIe designs. Resolved problem related to Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT having link up issue Resolved problem related to IEEE 802.3-2022 50GBASE-KR compliance testing marginality during Link Training (LT). Resolved problem related to FGT transceivers using certain FGT Attribute Access method sequence hanging. Firmware version 1.15fw: Added Safe SEU error injection mailbox command. Please also see the following links: Updating the SDM Firmware in the Agilex® FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.