Why does Agilex® 7 FPGA M-Series fail to be reconfigured after applying a software cold reset from U-Boot proper in Quartus® Prime Pro release 26.1?
Description Due to an incorrect implementation of the cold reset flow in U-Boot proper, in Agilex® 7 FPGA M-Series in release 26.1, the FPGA/JTAG is not kept in a clean idle state, resulting in the JTAG reconfiguration rejection. This causes the following error observed when you try to reconfigure the device after the cold reset: SOCFPGA_AGILEX7M # reset resetting ... Mailbox: Issuing mailbox cmd REBOOT_HPS rolando@rolando3-linux-lab:~/tasks/testbin$ quartus_pgm -c 1 -m jtag -o "p;ghrd.hps.rbf@2" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 26.1.0 Build 110 03/26/2026 SC Pro Edition Info: Copyright (C) 2026 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Tue Jun 30 18:42:30 2026 Info: System process ID: 93542 Info: Command: quartus_pgm -c 1 -m jtag -o p;ghrd.hps.rbf@2 Info (213046): Using programming cable "Intel Agilex M-Series Development Kit - HBM2e Edition on AN04WVAW035PS.an.altera.com [1-12]" Info (213011): Using programming file ghrd.hps.rbf with checksum 0xA66FE7E5 for device AGMF039R47AC@2 Info (209060): Started Programmer operation at Tue Jun 30 18:42:32 2026 Info (18942): Configuring device index 2 Error (18952): Error status: Device does not accept configuration request Error (18939): Unexpected error in JTAG server: JTAG chain broken Error (18952): Error status: Detected error when rescan jtag chain Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue Jun 30 18:42:43 2026 Error: Quartus Prime Programmer was unsuccessful. 4 errors, 0 warnings Error: Peak virtual memory: 1235 megabytes Error: Processing ended: Tue Jun 30 18:42:43 2026 Error: Elapsed time: 00:00:13 Error: System process ID: 93542 Resolution To work around this problem, you can disable the watchdog timer before issuing the cold reset. This can be done using the wdt stop command from the U-Boot shell as shown next: SOCFPGA_AGILEX7M # wdt list watchdog@ffd00200 (designware_wdt) SOCFPGA_AGILEX7M # wdt dev watchdog@ffd00200 SOCFPGA_AGILEX7M # wdt stop SOCFPGA_AGILEX7M # reset Note: You need to build your U-Boot to support the wdt command by setting CONFIG_CMD_WDT=y in your build configuration. You can also apply the cold reset from Linux, in which the error is not observed. For this, you can use the reboot command from the Linux shell. This problem will be fixed in a future release.Why does the Simulation Library Compiler fail due to a missing km_220model.sv file in Quartus® Prime Pro Edition 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, the Simulation Library Compiler might fail when compiling simulation libraries for a supported third-party simulator (for example Aldec Riviera-PRO*, Siemens EDA QuestaSim*, or Cadence Xcelium*) if you compile libraries using RTL-only or Compatible Mode for Quartus simulation flow without selecting a specific device family. The compile might stop with an error that a simulation source file such as km_220model.sv cannot be found under the Quartus installation quartus/eda/sim_lib directory. Example errors: Cannot find source file: <Quartus installation>/quartus/eda/sim_lib/km_220model.sv Failed to open design unit file km_220model.sv in read mode. This occurs because the Simulation Library Compiler requests certain simulation model files that are not included in the Quartus® Prime Pro Edition software version 26.1 installer. Those model files are not required to simulate designs that target currently supported device families. Libraries that already compiled successfully before the error remain valid. Refer to the Quartus Prime Pro Edition User Guide: Third-party Simulation (document ID: 683870). Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 26.1, follow these steps: Open a command prompt or terminal where the Quartus Prime software and your simulator license are available. Re-run the Simulation Library Compiler and specify your target device family with the -family option. Do not use an RTL-only compile that omits -family when you only need libraries for one device family. Example (Aldec Riviera-PRO, Verilog, Quartus-compatible mode): quartus_sh --simlib_comp -tool rivierapro -language verilog -mode quartus -family "Arria 10" -tool_path <path_to_riviera_bin> -directory <output_directory> Replace Arria® 10 FPGA with your device family name. Run quartus_sh --help=simlib_comp to list valid -family values for your install. Alternatively, in the Quartus Prime software GUI: Click Tools > Launch Simulation Library Compiler. Select your simulation tool, HDL language, target device family, and output location. Start Compilation. If you must keep an RTL-only or all-library compile on version 26.1 only: Create an empty placeholder file named km_220model.sv in <Quartus installation>/quartus/eda/sim_lib/. Re-run the Simulation Library Compiler. If the compile reports another missing file under sim_lib with a similar name pattern, create an empty placeholder for that file and continue. This problem is fixed in the Quartus® Prime Pro Edition Software version 26.3.Why does the F-Tile Low Latency 100G Ethernet IP not work when Ready Latency is set to 3?
Description Due to a problem in the Quartus Prime Pro Edition software version 26.1, you may see the F-Tile Low Latency 100G Ethernet IP doesn’t work when the IP for Ready Latency is set to 3 and it may result in incorrect TX client interface behavior because the Ready Latency parameter is not fully propagated through the generated IP hierarchy. There is no workaround in the current IP implementation because the Ready Latency GUI parameter is not used in the generated IP. Resolution A 26.1 patch (0.32) is available for this problem and it is attached to this article. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does Test Engine driver synchronization fail when Memory AXI4 drivers use different clock frequencies?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 26.1 and earlier, Driver Synchronization between Test Engine Memory AXI4 drivers does not work correctly when the drivers use different clock frequencies. When using post and wait commands across drivers with different clock frequencies, you may observe one of the following behaviors: A post command from a slower driver causes the faster driver to skip multiple wait commands. A post command from a faster driver causes the slower driver to hang and fail to continue from the wait command. Traffic patterns that do not use post or wait commands are not affected. Resolution There is no workaround for this problem. Use Driver Synchronization only when all synchronized drivers use the same clock frequency.Why does configuration occasionally fail on Agilex® 7 FPGA devices, leaving the device stuck in the CONFIG state when using a JIC file generated with Quartus® Prime Pro Edition version 23.2 or later?
Description You may encounter intermittent configuration failures on the Agilex® 7 FPGA device, when using JIC file generated with Quartus® Prime Pro Edition software version 23.2 and later. When the issues occurs, the device remain in the CONFIG state, while both the conf_done and init_done is remain low. In addition, no error location and error info as shown below. Resolution To work around this issues: Power cycle the board or toggle nCONFIG to reconfigure the FPGA. Patches are also available to fix this problem for the following Quartus Prime Pro Versions: 23.2 23.3 This problem is fixed starting from Quartus Prime Pro Edition Version 25.1.1 and later. Additional Information Note: If you can tolerate occasional errors that are unlikely to recur after reconfiguration, no further action is necessary. If you require zero-error tolerance—even for rare occurrences that may be resolved through reconfiguration or toggling nCONFIG—a patch request is recommended. This fix does not require recompilation of the design. You only need to reconvert the .sof file to .jic. Add any additional information on the topic. Related Articles Why does configuration fail intermittently when using a JIC file generated with Quartus® Prime Pro Edition version 23.2 and later on Agilex® 7 FPGA devices, resulting in Major Error Code 0x0000F004 and Minor Error Code 0x00000001? | Altera Community - 339342How do I enable debug endpoint for transceiver toolkit (ADME) for the F-Tile 25G Ethernet Soft-IP to use the Transceiver Toolkit?
Description The F-Tile 25G Ethernet IP (alt_e25_f) does not expose the "Enable debug endpoint for transceiver toolkit" option in the IP Parameter Editor GUI. As a result, users cannot enable Transceiver Toolkit access through the standard IP configuration interface. Resolution To enable debug endpoint for transceiver toolkit for the F-Tile 25G Ethernet IP, use the following workaround: To enable the debug endpoint for the Transceiver Toolkit, use the following workaround: Open the .ip file for the F-Tile 25G Ethernet Soft IP. Locate the ENABLE_ADME_GUI parameter. Change its value from 0 to 1. Save the .ip file. Regenerate the IP. Note: This workaround modifies a hidden parameter that is not officially available in the GUI. The parameter implementation may change in future releases. After upgrading Quartus® Prime software, verify that the functionality continues to operate as expected.Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3, 25.3.1 and 26.1, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User MSI-X option is selected under the PCIe Settings --> MCDMA Settings tab The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: add_connection GEN_CHK_M0.usr_msix DUT.user_msix: Cannot connect GEN_CHK_M0.usr_msix to DUT.user_msix. Error: Failed to generate example design example_design to: <path> This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User MSI-X option is selected. Resolution To work around this problem, do not select the Enable User MSI-X option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* Example Design. There is no other workaround for Quartus Prime Pro Edition Software versions 25.3, 25.3.1, and 26.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example with the Packet Generate/Check variant may fail when using the Siemens Questa* simulator. The failure is observed after the DMA queue reset sequence finishes, and a PIO register write is issued. Simulation then stalls with no further activity and terminates with an inactivity timeout after some time. An example of the messages observed in the simulation log is shown below: INFO: 43000 ns H2D: Got Status for Channel 0 INFO: 43000 ns D2H: Performing Channel 0 Queue Reset INFO: 47000 ns D2H: Channel 0 Queue Reset...done INFO: 47000 ns PIO_WRITE_REG 8000000100001000 FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! ** Note: $stop : ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v(146) Time: 4 ms Iteration: 3 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/u1/rp/inst/apps/genblk1/drvr Break at ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v line 146 This issue affects simulation only and does not impact hardware functionality. Resolution To work around this problem, generate the F-Tile Multi Channel DMA FPGA IP for PCI Express Design Example (Packet Generate/Check variant) and run simulation using Quartus® Prime Pro Edition Software version 25.1.1. The problem is not observed in that release. There is no other workaround for Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3 and later, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User FLR option is selected under the PCIe Settings --> MCDMA Settings tab. The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: pcie_axi_mcdma_0: Fail .qsys synthesis generation Error: pcie_axi_mcdma_0: Unable to generated HDL Files for the system .qsys Error: Failed to generate example design example_design to: <path> Generate Example Design: completed with errors. This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User FLR option is selected. Resolution To work around this problem, do not select the Enable User FLR option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design. There is currently no other workaround for Quartus® Prime Pro Edition Software versions 25.3 and later. This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software.
