Knowledge Base Article
Why is data transfer performance low when using the HPS DMA Controller?
Description
Due to the design of the Hard Processor System (HPS) Direct Memory Access Controller (DMAC) in Altera FPGA Agilex® 7, Agilex® 5, and Agilex® 3 devices, data transfer throughput across the HPS-to-FPGA (H2F) and Lightweight HPS-to-FPGA (LWH2F) bridges can appear low-sometimes as low as approximately half of the theoretical maximum-when you use the HPS DMAC for transfers via the H2F or LWH2F path.
The generic DMA controller in the HPS is optimized and sized for peripheral data movement within the HPS complex and may not move data near the maximum theoretical throughput across the H2F or LWH2F bridges.
Resolution
To work around this limitation when higher throughput is required between the HPS and FPGA fabric, follow these steps:
- Evaluate a fabric-based DMA controller for data transfers between the HPS and FPGA fabric.
- Measure the resulting throughput against your application bandwidth requirements to determine whether the fabric-based DMA meets your needs.
This behavior reflects HPS DMAC sizing for bridge traffic; it is not scheduled to be changed in a Quartus® Prime software release.