Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does Arria® 10 HPS IP generation fail with missing mgc_common_axi.sv in Quartus® Prime Pro 24.1/24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, Arria® 10 HPS IP generation may fail with an error similar to: Error: add_fileset_file: no such file .../ip/altera/mentor_vip_ae/axi3/bfm/mgc_common_axi.sv This occurs because AXI3 Mentor Graphics BFM collateral was removed starting in Quartus Prime Pro 24.1, while the Arria 10 HPS generation flow still referenced the removed AXI3 BFM file. Associated Quartus Suite bug: QS-569165. Resolution To resolve this issue, upgrade to Quartus Prime Pro Edition Software version 24.3, regenerate the Platform Designer system/IP output files, and rerun compilation.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why are some simulation library files missing when compiling for Questasim*?
Description Due to a problem in Simulation Library Compiler in the Quartus® Prime Standard Edition Software 23.1 and later, you may see some Quartus® Simulation Library source files not included for compilation for Siemens* Questasim* Tool selection. This problem persists on both EDA Simulation Library Compiler GUI and command line versions. This problem only exists in Quartus® Prime Standard Edition and does not affect Quartus® Prime Pro Edition versions. Resolution To work around this problem, follow these steps: 1. Edit file: <QUARTUS INSTALLATION DIRECTORY>/quartus/common/tcl/internal/simlib_comp.tcl 2. Replace: set gl(primary_tool,questasim) questasim With: set gl(primary_tool,questasim) modelsim This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the outclk of the ALTCLKCTRL IP remain enabled when using the ENA input in External Path mode?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 or earlier, you might see that the output clock of the ALTCLKCTRL IP remains enabled regardless of whether the ENA input is asserted or de‑asserted when using the “External path” mode. This problem occurs because the ENA input port is not used in “External path” mode even if the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option is selected. Beginning with the Quartus® Prime Standard Edition Software version 23.1, the software will generate an error message indicating that the “Create ‘ena’ port” option is unavailable when the “External path” type is selected. Resolution To work around this problem using the ALTCLKCTRL IP with the “External path” mode: Disable the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option in the Parameter Editor. If you require clock gating, implement the gating logic external to ALTCLKCTRL (for example, gate the source clock or use an alternate supported clock‑control scheme) rather than relying on the ALTCLKCTRL ENA port in “External path” mode.