Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 5 and Agilex™ 3 SoC FPGAs when using Quartus® Prime Pro Edition Software version 25.3.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1, Phase 2 configuration (FPGA fabric configuration from HPS) may fail on Agilex™ 5 and Agilex™ 3FPGA devices when Phase 1 and Phase 2 bitstreams originate from different designs or design revisions. This is caused by HPS IO hash mismatches between compilations. Resolution To work around this problem, download and install the patch below. You must recompile both the design generating the Phase 1 bitstream and the design generating the Phase 2 bitstream using the patched version of Quartus® Prime Pro Edition Software version 25.3.1. Additional Information HPS IO hash mismatches can also occur for other reasons independent of this Quartus® Prime Pro Edition Software problem. For more information about other potential causes and how to avoid them, refer to the HPS IO Hash Compatibility section in the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCsWhy does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does Nios® V/c processor fail to service interrupts when it is under CLINT-Vectored mode?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, the Nios ® V/c processor might fail to service any interrupts when it is under CLINT-Vectored mode. The affected interrupts are platform interrupts, software interrupt, and timer interrupt. The following are not affected by this issue: Nios ® V/c processor under CLINT-Direct, Nios ® V/m processor, and Nios ® V/g processor This is because the Board Support Package Editor fails to generate relevant macros in system.h to support CLINT-Vectored mode. Resolution To continue using CLINT-Vectored with Nios ® V/c processor, add the following macros in the system.h. #define ALT_CPU_INT_MODE 1 #define NIOSVSMALLCORE_INT_MODE 1 #define INTEL_NIOSV_C_0_DM_AGENT_INT_MODE 1 This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why is there a failure in the design if we are doing design migration for Agilex™ 3/Agilex™ 5 FPGA, with GTS Reset Sequencer from version 25.3 to 25.3.1?
Description Following an IP upgrade from version 25.3 to version 25.3.1 of the Quartus® Prime Pro Edition software, there is a port renaming involved for Agilex™ 3 FPGAS or Agilex™ 5 FPGA GTS Reset Sequencer IP. There are two ports that has been renamed for improvement purpose. Resolution For a workaround, you need to update the existing port name to the new ports that are available in the GTS Reset Sequencer IP. The existing ports that will require update are: i_src_rs_refclk_status_bus_out (25.3) --> i_src_rs_refclk_status_bus (25.3.1) o_src_rs_refclk_status_bus_in (25.3) --> o_src_rs_refclk_status_bus (25.3.1)Why is there a fitter failure when using reference clock from HVIO System PLL for FABRIC_USE_CASE in the Agilex™ 3/ Agilex™ 5 FPGA GTS System PLL Clocks IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, user will encounter fitter failure when they are using HVIO Reference Clock for Fabric_Use_Case. Resolution For a workaround, you need to set location assignment based on your selected devices in QSF assignment: Agilex™ 5 Family and Series Density Device Group Package Code Location Assignment A5E 013 A/B B23A/B32A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] A5E 028 A/B B23A/B23A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] 1B [SMHSSIPLLWRAP_X0_Y54_N1956] 4A [SMHSSIPLLWRAP_X121_Y7_N1956] A5E 065 A/B B23A/B32A 1A: [SMHSSIPLLWRAP_X121_Y7_N1956] 1B: [SMHSSIPLLWRAP_X0_Y54_N1956] 1C: [SMHSSIPLLWRAP_X0_Y101_N1956] 4A: [SMHSSIPLLWRAP_X185_Y7_N1956] 4B [SMHSSIPLLWRAP_X185_Y54_N1956] 4C [SMHSSIPLLWRAP_X185_Y101_N1956] A5D 064 A/B B32A 1A [SMHSSIPLLWRAP_X0_Y7_N2406] 1B [SMHSSIPLLWRAP_X0_Y15_N2406] 1C [SMHSSIPLLWRAP_X0_Y99_N2406] 1D [SMHSSIPLLWRAP_X0_Y107_N2406] 4A [SMHSSIPLLWRAP_X159_Y7_N2406] 4B [SMHSSIPLLWRAP_X159_Y15_N2406] 4C [SMHSSIPLLWRAP_X159_Y99_N2406] 4D [SMHSSIPLLWRAP_X159_Y107_N2406] This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why is there "sopcinfo2swinfo.exe: command not found" when running sopc-create-header-files under WSL, or Docker under Windows?
Description An error message like this: sopc-create-header-files: line 182: sopcinfo2swinfo.exe: command not found sopc-create-header-files: sopcinfo2swinfo.exe --input=./peripheral_subsys.sopcinfo --output=/tmp/sopc-create-header-files.1312.tmp.swinfo failed will be seen in the Quartus ® Prime Pro Edition Software version 25.3.1 and earlier, when using the sopc-create-header-files script within the Linux version of the Quartus ® Prime Pro Edition Software, running on the Microsoft* Windows operating system. The Linux version of the tools can be installed under Windows* using WSL, WSL2 or Docker. In all of these cases, the sopc-create-header-files script detects that it is running under Windows* and looks for an internal tool with the suffix “.exe”. However, since the Linux version has been installed, the tool does not have that suffix and so cannot be found by the sopc-create-header-files script. Resolution To work around the problem, either switch to using a Windows* installation of the Quartus® Prime Pro Edition Software, or follow these steps to continue using the Linux installation under Windows*: Under Linux, use the command “which sopc-create-header-files” to find the location of the script. Copy the script from this location to another location of your choice. Make the newly copied script version writable using the command: chmod +w <path to newly copied script> Modify your newly copied script version. Find the following line: windows_exe=.exe and either remove it or add a single # symbol at the start to comment it Use your newly modified version of the script instead of the installed version. This will now execute correctly.Why does Agilex™ 5 /Agilex™ 3 FPGAs fail to boot from SD Card in DDR50 mode?
Description Due to CRC errors observed in the SD Card interface, Agilex™ 5/Agilex™ 3 FPGA devices may fail to boot from SD Card when the SD/eMMC controller is in DDR50 mode. The failures observed could show “IO error, dev mmcblk0” errors or problems trying to read the partition table in the SD Card. This problem also leads to unreliable storage in the SD Card. If you can boot to Linux* shell in this mode and you want to confirm that you are facing this problem, you can get the CRC error count using the command: cat /sys/kernel/debug/mmc0/err_stats Resolution At this time, there is no workaround for this issue, but it is recommended to operate your SD card device in higher speed modes like SDR104. This problem may be fixed in a future release.Why do I get the error Internal Error "No Active Family" when trying to generate a programming JAM file via command line "quartus_pfg"
Description When trying to generate a JAM programing file (.jam) via the quartus_pfg command line from a Chain Description File (.cdf). quartus_pfg -c <file>.cdf <file>.jam You may get the following error message: Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_jam.cpp, Line: 2873 No Active Family Stack Trace: Quartus 0x3cce3e: PGMIO_JAM::jam2_filter(int, PGMIO_JTAG_UNI_ENGINE*, std::basic_ifstream >&, std::ostream&) + 0x582 (pgm_pgmio) Quartus 0x3d0a7a: PGMIO_JAM::jam2_create_file(int, PGMIO_JTAG_UNI_ENGINE*) + 0x846 (pgm_pgmio) Quartus 0x3d4ec2: PGMIO_JAM::create_output_file(std::vector >*, FIO_PATH const&, bool) + 0x3e8c (pgm_pgmio) This error may be due to an issue were the source programming files on the .cdf file not being valid. Resolution To work around this problem, verify your programing source file or files with the following command line: quartus_pfg -i <source>.sof This command will help you determine if your source file or files are valid and invalid and provide additional info on the issues with the invalid files for troubleshooting. Replace the invalid files with valid ones once identified.Why does the Synchronous FIFO Parameterizable Macro (sync_fifo) incorrectly output all zeroes data after being empty?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 or earlier, you might see that the first output data from the FIFO after the FIFO has been empty is incorrectly set to zero. This problem occurs when using the Synchronous FIFO Parameterizable Macro (sync_fifo) in show-ahead mode. Resolution To work around this problem, instantiate the FIFO FPGA IP instead of the Synchronous FIFO Parameterizable Macro. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
