Why does Vendor Authorized Boot (VAB) certificate authentication failed in SDM?
Description During the Second-Stage Bootloader (SSBL), you may encounter an intermittent timeout while transferring the initial 32‑word block of the VAB certificate command Error message displayed: #ret = 0x000007ff, resp = 0x00000000, resp_len = 1 #VAB certificate authentication failed in SDM #### ERROR ### Please RESET the board ### Resolution To avoid this problem, upgrade the socfpga_v2.12.1 (socfpga_mailbox.c) An ATF patch for socfpga_v2.12.1 is available to fix this problem : Download and install patch mbox.patch from the attachment below. This problem is scheduled to be resolved in a future ATF releasedWhy did the FCS client fail to verify the Vendor Authorized Boot (VAB) file?
Description You might see this error when performing a VAB file verification via fcs_client (e.g., signed-bl31.bin , u-boot.itb, kernel.itb). command for read out session ID: ./fcs_client -e command for perform verification : ./fcs_client –V <bitstream.vab> -s <sessionID> --loglevel=4 Error message display, when verified signed-bl31.bin: root@agilex7dksiagf014eb:~# ./fcs_client -V signed-bl31.bin -s 869f2929-c2d3-b64a-bbc7-c003718d60ed --loglevel=4 [ 2831.587900] Session UUID Mismatch ret: -22 [ 2831.592065] Failed to initialize digest ret: -22 [ 2831.596698] Failed to perform get digest update [err:]Failed to write to sysfs attribute [err:]Error in getting digest [err:]Error in calculating image hash [err:]Error in verifying image hash noffset=0 Error message display, when verified u-boot.itb/kernel.itb: root@agilex7dksiagf014eb:~# ./fcs_client -V u-boot.itb-s 869f2929-c2d3-b64a-bbc7-c003718d60ed --loglevel=4 [err:]Error in getting image data noffset = Resolution To solve this problem, you will need install the patch for libfcs: fix-image-validation-issues3.patch This problem is scheduled to be resolved in a future release of the libfcs.How can I tell if a Raw Binary File (.rbf) is a PR Bitstream File?
Description A customer can tell if a Raw Binary File (.rbf) is a PR Bitstream File by following the information below. Resolution A PR Bitstream will start with the value 0x97566593 at offset 0x000 AND Have the value 0x5052(PR) at offset 0x00C.Why does Partial Reconfiguration (PR) via HPS fail only when using encrypted PR bitstreams?
Description Partial Reconfiguration (PR) via HPS fails only when using encrypted PR bitstreams. This failure only happened on encrypted PR bitstream and not base bitstream. Error message display: root@agilex:~# mv /tmp/pr.rbf /lib/firmware/persona0.rbf root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_fpga_static_region.dtbo Applying dtbo: /lib/firmware/agilex7_pr_fpga_static_region.dtbo [ 251.625026] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/ranges [ 251.638872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/external-fpga-config [ 251.649792] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clocks [ 251.659426] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clock-names [ 251.669543] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0 [ 251.679105] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0 [ 251.693803] of-fpga-region fpga-region:fpga_pr_region0: FPGA Region probed root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_persona0.dtbo Applying dtbo: /lib/firmware/agilex7_pr_persona0.dtbo [ 262.265981] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager [ 267.497950] Stratix10 SoC FPGA manager firmware:svc:fpga-mgr: timeout waiting for svc layer buffers Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition software.Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, you might see this error when compiling your design in Design Space Explorer II. Error: Tcl error: DVR_API: List of error MSGs are {list element in braces followed by "]" instead of space (Command was: lmap panel_name [::qed_lib::rdb_util::get_report_panel_names_matching -panel_name {} -string_match {Synthesis||Logic Synthesis Stage||Partition*||*Optimization Results||Multiplier Implementations||Multiplier Implementation Report} -regexp_match {}] {::qed_lib::rdb_util::get_report_panel_str -panel_name $panel_name})} Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.21 This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the SD/eMMC U-Boot driver fail to select the SDR12 mode for Agilex® 5 FPGA and Agilex® 3 FPGA devices in release 25.3.1 release and before?
Description Due to a problem in the U-Boot SD/eMMC driver in Agilex® 5 FPGA and Agilex® 3 FPGA devices in release 25.3.1 and before, U-Boot fails to select the SD SDR12 mode regardless of using the sd-uhs-sdr12 parameter in the device tree. The reason behind this problem is that the driver tries the SD_HS (50 MHz) mode first, so if this succeeds, then the SDR12 (25 MHz) is not tried. Because of this problem, currently, there is no direct method to force the driver to choose SDR12 mode. Resolution To workaround this problem, you need to use the following configuration in the device tree along with the SD/eMMC driver source code modification: 1. U-Boot device tree configuration: Remove no-1-8-v: Allows the MMC stack to perform voltage switching to 1.8V, which is required for UHS modes Remove cap-sd-highspeed: Ensures SDR12 becomes the highest priority mode available Add sd-uhs-sdr12: Explicitly declares SDR12 support &mmc { status = "okay"; no-mmc; disable-wp; //no-1-8-v; // Remove or keep commented out //cap-sd-highspeed; // Remove or keep commented out sd-uhs-sdr12; // Add this property vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&sd_io_1v8_reg>; max-frequency = <200000000>; sdhci-caps = <0x00000000 0x0000c800>; sdhci-caps-mask = <0x00002007 0x0000ff00>; // ... (rest of PHY timing configuration remains unchanged) }; 2. Modify the U-Boot drivers/mmc/sdhci-cadence.c source code as follows: You must update the host->quirks parameter to disable the SD High Speed mode at the driver level, providing an additional safeguard to ensure SDR12 is selected. static int sdhci_cdns_probe(struct udevice *dev) { : host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; // Add this line : } This problem will be fixed in a future release.
Generation of AOCL Report Failed with below error
Description Due to a problem in the FPGA Support Package for the oneAPI DCP++/C++ Compiler version 2024.2, you might see this error. Generation of AOCL Report Failed with the below error PLEASE submit a bug report to https://software.intel.com/en-us/support/priority-support and include the Stack dump: … aocl-opt 0x0000XXXXXXXXXXXX llvm::AccessGroupInfo::hasIndependentAGsOrSafelen(llvm::Loop*, llvm::Instruction*, llvm::Instruction*, int&) + 195 … or … aocl-opt: XXXXXXXX: llvm::Value::~Value(): Assertion `materialized_use_empty() && "Uses remain when a value is destroyed!"' failed. … Resolution To work around this problem, download and install the 2024.2.1 patch for the FPGA Support Package below. Determine where the 2024.2 Intel oneAPI DCP++/C++ Compiler is installed. The FPGA Support Package will be located inside of the compiler installation directory in the ‘oclfpga’ folder. For Linux, this will be ‘<install-dir>/intel/oneapi/compiler/2024.2/opt/oclfpga’, where <install-dir> is typically either ‘/opt’ or ‘~’. For Windows, this will usually be ‘C:\Program Files (x86)\Intel\oneAPI\compiler\2024.2\opt\oclfpga’. Rename the existing ‘oclfpga’ directory to something else, e.g., ‘oclfpga.bak’ or ‘oclfpga.prev’. Unpack the given archive, .tar.gz for Linux and .zip for Windows, to extract the ‘oclfpga’ folder and place it in ‘intel/oneapi/compiler/2024.2/opt’. (Optional) Remove the backup folder created in Step ‘2’ after testing. This problem is scheduled to be fixed in a future release of the FPGA Support Package for the oneAPI DCP++/C++ Compiler.Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex™ FPGAs family SDM I/O pins after long-term operation?
Description On all Stratix® 10 FPGA and Agilex™ FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues. Resolution Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus. Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.
