Knowledge Base Article
Why is there a fitter failure when using reference clock from HVIO System PLL for FABRIC_USE_CASE in the Agilex™ 3/ Agilex™ 5 FPGA GTS System PLL Clocks IP?
Description
Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, user will encounter fitter failure when they are using HVIO Reference Clock for Fabric_Use_Case.
Resolution
For a workaround, you need to set location assignment based on your selected devices in QSF assignment:
|
Agilex™ 5 Family and Series |
Density |
Device Group |
Package Code |
Location Assignment |
|
A5E |
013 |
A/B |
B23A/B32A/ M16A |
For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] |
|
A5E |
028 |
A/B
|
B23A/B23A/ M16A |
For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] 1B [SMHSSIPLLWRAP_X0_Y54_N1956] 4A [SMHSSIPLLWRAP_X121_Y7_N1956] |
|
A5E |
065 |
A/B
|
B23A/B32A |
1A: [SMHSSIPLLWRAP_X121_Y7_N1956] 1B: [SMHSSIPLLWRAP_X0_Y54_N1956] 1C: [SMHSSIPLLWRAP_X0_Y101_N1956] 4A: [SMHSSIPLLWRAP_X185_Y7_N1956] 4B [SMHSSIPLLWRAP_X185_Y54_N1956] 4C [SMHSSIPLLWRAP_X185_Y101_N1956]
|
|
A5D |
064 |
A/B
|
B32A |
1A [SMHSSIPLLWRAP_X0_Y7_N2406] 1B [SMHSSIPLLWRAP_X0_Y15_N2406] 1C [SMHSSIPLLWRAP_X0_Y99_N2406] 1D [SMHSSIPLLWRAP_X0_Y107_N2406] 4A [SMHSSIPLLWRAP_X159_Y7_N2406] 4B [SMHSSIPLLWRAP_X159_Y15_N2406] 4C [SMHSSIPLLWRAP_X159_Y99_N2406] 4D [SMHSSIPLLWRAP_X159_Y107_N2406] |
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.