Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why does internal serial loopback test results fail when running the GTS JESD204B FPGA IP Design Example on Agilex™ 3 FPGA or Agilex™ 5 FPGA hardware?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter a failed test result when running the internal serial loopback test with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install patch below. After installing the patch, do the following: In the GTS JESD204B IP GUI editor, IP > Main tab, enabled the following checkboxes: Enable PMA Avalon memory-mapped interface Enable control and status registers Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Warning(332174): Ignored filter at alt_sld_fab_0_st_dc_fifo_<unique ID>.sdc(Line number): *|in_wr_ptr_gray[*] could not be matched with a register
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see 'ignored filter' SDC warnings when your design includes the Partial Reconfiguration External Configuration Controller IP. Resolution This warning is safe to ignore and is scheduled to be removed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core Partial Reconfiguration External Configuration Controller IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why doesn’t Quartus® Prime Pro Edition Software version 25.3 generate programming files for my Agilex™ FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might not be able to generate programming files for some Agilex™ 5/3 FPGA devices. Here is the list of impacted OPNs: A5EG005BB18AE4S A5EG005BB18AE5S A5EG005BB18AE6S A5EG005BB18AE6X A5EG005BB18AI4S A5EG005BB18AI5S A5EG005BB18AI6S A5EG005BB18AI6X A5EG007BB18AE4S A5EG007BB18AE5S A5EG007BB18AE6S A5EG007BB18AE6X A5EG007BB18AI4S A5EG007BB18AI5S A5EG007BB18AI6S A5EG007BB18AI6X A3CZ025BB18AE7S A3CZ025BB18AI7S A3CZ050BB18AE7S A3CZ050BB18AI7S A3CZ065BB18AE7S A3CZ065BB18AI7S Resolution If you are using any of the listed devices in your design, download and install the patches below to enable programming file generation in Quartus® Prime Pro Edition Software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does the Agilex™3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, fail during simulation using Xcelium* and Riviera*-PRO simulators in Quartus® Prime Pro Edition Software version 25.1.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the Agilex™ 3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, may fail during simulation of the design example testbench. The following behaviors may be observed: Riviera*-PRO: Simulation may hang or display "Error: Accuracy criteria not met". Xcelium*: Simulation may pass, but accuracy criteria will not be met, leading to incorrect results. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software Version 25.1.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?
Description Due to a silicon problem in Agilex™ 5 and Agilex™ 3 devices, the SRS16 capability register of the SDMMC controller incorrectly reports in the EDS8 bit (bit 18) that the controller does not support the eMMC 8-bit bus width mode. As a result, the U-Boot eMMC driver identifies 4-bit mode as the maximum supported width and configures the controller accordingly. This occurs even if the bus-width parameter is explicitly set to 8 in the device tree. Resolution To work around this problem, use the sdhci-caps and sdhci-caps-mask parameters in the U-Boot device tree to override the incorrectly reported values in the capability registers (SRS16 and SRS17). For this case, override bit 18 in SRS16 to indicate that an 8-bit bus width is supported. Example configuration: &mmc { status = "okay"; bus-width = <8>; sdhci-caps = <0x00000000 0x00040000>; sdhci-caps-mask = <0x00000000 0x00040000>; sd-uhs-sdr50; cap-mmc-highspeed; bootph-all; }; Verification in U-Boot: After applying the workaround, you can verify that the controller is using an 8-bit bus width by running the mmc info command: SOCFPGA_AGILEX5 # mmc info Device: mmc0@10808000 Manufacturer ID: 13 OEM: 4e Name: G1M15L Bus Speed: 52000000 Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 29.6 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 29.6 GiB WRREL Boot Capacity: 31.5 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected This workaround will be permanently implemented in the Agilex™ 5/Agilex™ 3 U-Boot device tree in a future release of the FPGA HPS Embedded Software.How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?
Description Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically: Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function. Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it. Resolution To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows: Incorrect Pin Index Correct Pin Index 10/11 0/1 22/23 12/13 34/35 24/25 46/47 36/37 Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner. This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.Why does the GTS JESD204B/C FPGA IP and Design Example generation fail on Agilex™ 3 FPGA and Agilex™ 5 FPGA devices when selecting System or HVIO PLL clocking mode?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter an error message like the following when generating the GTS JESD204B/C FPGA IP Design Example. "Error: phy_inst.inst_directphy: System/HVIO PLL frequency "307.2" cannot be smaller than transceiver's parallel clock frequency "858.0" The following IP configuration steps may lead to the above error: Set the Data rate to a specific value Set the Datapath clocking mode System PLL Enable the example design generation Enable Simulation and/or Synthesis in the Example Design Files section Increase the data rate to a value higher than the data rate set in step 1 Generate the IP or Example Design *Note that this problem will not occur when you use a data rate set in Step 5 lower than the data rate set in Step 1. Resolution When you encounter this error, use the following workaround: Disable example design generation Update the System PLL frequency for the latest data rate Enable example design generation Generate the IP or Example Design This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.