Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Why doesn’t Quartus® Prime Pro Edition Software version 25.3 generate programming files for my Agilex™ FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might not be able to generate programming files for some Agilex™ 5/3 FPGA devices. Here is the list of impacted OPNs: A5EG005BB18AE4S A5EG005BB18AE5S A5EG005BB18AE6S A5EG005BB18AE6X A5EG005BB18AI4S A5EG005BB18AI5S A5EG005BB18AI6S A5EG005BB18AI6X A5EG007BB18AE4S A5EG007BB18AE5S A5EG007BB18AE6S A5EG007BB18AE6X A5EG007BB18AI4S A5EG007BB18AI5S A5EG007BB18AI6S A5EG007BB18AI6X A3CZ025BB18AE7S A3CZ025BB18AI7S A3CZ050BB18AE7S A3CZ050BB18AI7S A3CZ065BB18AE7S A3CZ065BB18AI7S Resolution If you are using any of the listed devices in your design, download and install the patches below to enable programming file generation in Quartus® Prime Pro Edition Software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Warning(332174): Ignored filter at alt_sld_fab_0_st_dc_fifo_<unique ID>.sdc(Line number): *|in_wr_ptr_gray[*] could not be matched with a register
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see 'ignored filter' SDC warnings when your design includes the Partial Reconfiguration External Configuration Controller IP. Resolution This warning is safe to ignore and is scheduled to be removed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core Partial Reconfiguration External Configuration Controller IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does the HPS in Agilex™ 5 FPGA/Agilex™ 3 FPGA fail to load components from the QSPI device when the hardware design or SDM FW comes from Quartus® Prime Pro 25.1 and later?
Description Due to the QSPI Ownership Selection feature introduced in Quartus® Prime Pro 25.1, the HPS request for the ownership of the QSPI via the QSPI_DIRECT command can be either accepted or rejected by the SDM firmware. This request typically occurs during the FSBL stage, and the SDM firmware decides to reject or accept the request based on the QSPI Ownership setting defined in the hardware design. This affects scenarios such as Remote System Update (RSU), where the RSU components reside in the QSPI device, as well as any other boot flow that relies on the HPS loading components from QSPI, such as HPS booting from QSPI. The QSPI Ownership feature is not backward-compatible. Mixing .sof files generated from Quartus® Prime Pro versions prior to 25.1 with SDM firmware from 25.1 or later (and vice versa) may cause compatibility issues. This problem can also be observed when porting a hardware design from a Quartus® Prime Pro version prior to 25.1 to a newer version, because by default, Quartus® Pro assigns the QSPI ownership to the SDM. Resolution To avoid this problem, follow the recommendations provided below. In RSU scenarios, do not mix applications created with Quartus® Prime Pro versions prior 25.1 with applications created with 25.1 or later. Do not mix. .sof hardware designs created with Quartus® Prime Pro versions prior 25.1 with SDM FW from Quartus® Prime Pro 25.1 and later, and vice versa. In new hardware designs whose boot flow depends on the HPS loading components from the QSPI device or when porting these from Quartus® Prime Pro versions prior 25.1 to a more recent version, make sure to select the HPS as the QSPI owner in Quartus® configuration (from Assignments > Device > Device and Pin Options > QSPI Ownership configuration), because by default Quartus® assigns the QSPI ownership to SDM and missing this configuration will make HPS to fail to load these components. Additional Information For more information about this feature, you can refer to: A.2.2. HPS Use of SDM QSPI Controller Use Cases in n the Agilex5/Agilex 3 HPS Technical Reference Manual A.2.2.1. Feature Availability under SDM/HPS Ownership of Quad SPI Controller in n the Agilex5/Agilex 3 HPS Technical Reference Manual 4.2.1. Device and Pin Options in Agilex5/Agilex 3 HPS Booting User Guide 4.12. QSPI Controller Ownership Selection Impact on the HPS Software in Agilex5/Agilex 3 HPS Booting User GuideWhy True Differential input buffer with on-chip differential Termination (RD OCT) enabled does not respond after device is configured for Agilex™ 3 FPGA, Agilex™ 5 FPGA, and Agilex™ 7 FPGA devices?
Description The on-chip differential termination (RD OCT) for the True Differential input buffer is not enabled correctly in Quartus® Prime software. This issue impacts all True Differential Signaling (TDS) input buffer with RD OCT enabled, except when such input standard is used as the EMIF interface reference clock. Resolution This issue will be fixed progressively according to devices in the Quartus® Prime software. Refer to the tables below for the fix plan per device and Quartus® Prime version. Part Number Quartus® Prime v25.1 Quartus® Prime v25.1.1 Quartus® Prime v25.3 AGMxxxxxxxxxxVR0 Not Fixed Not Fixed Fixed AGMxxxxxxxxxxxVC Not Fixed Fixed Fixed A5Ex013xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex013xxxxxxxS/V/XCS/R1 A5Ex008xxxxxxxS/V/XCS/R1 Not Fixed Fixed Fixed A5Ex065xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex065xxxxxxxS/V/E/X A5Ex052xxxxxxxS/V/E/X A5Ex043xxxxxxxS/V/E/X Not Fixed Not Fixed Fixed A3CxxxxxxxxxxxS Not Fixed Fixed Fixed Alternatively, you may use the below .tcl script to fix the differential termination settings in your .sof file manually. Please contact Altera Support team for assistance.Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy does the INSERT_SAFE_SEU_ERROR command inject the SEU error into an incorrect location on Agilex™ 3 FPGA devices?
Description Due to a problem with the Quartus® Prime Pro Edition Software version 25.3, injecting an SEU error using the INSERT_SAFE_SEU_ERROR command on Agilex™ 3 FPGA devices may result in the READ_SEU_ERROR command reporting a location that does not match the predefined injection location. This incorrect SEU error location could potentially lead to functional errors in user designs. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 BYTE_CONTROL(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter the below fitter error when entering an odd number (1 or 3 or 5 or 7) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI when designing with the Agilex™ 3 FPGA or Agilex™ 5 FPGA MIPI D-PHY IP. Error(175001): The Fitter cannot place 1 BYTE_CONTROL, which is within Generic Component dphy_dut_dphy. Info(14596): Information about the failing component(s): Info(175028): The BYTE_CONTROL name(s): dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_control_wrap_inst|byte_control_inst Error(16234): No legal location could be found out of 32 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the BYTE_CONTROL and the BYTE_CONTROL Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175029): 16 locations affected Error(175006): There is no routing connectivity between the BYTE_CONTROL and destination BYTE Info(175027): Destination: BYTE dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_wrap_inst|byte_inst Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175021): The destination BYTE was placed in location BYTE_X126_Y147_N106 Info(175029): 16 locations affected Resolution To work around this problem, generate the MIPI D-PHY Design Example with only even number (0 or 2 or 4 or 6) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.
