Why do I unexpectedly observe intermittent DDM Errors?
Description Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus® Prime Pro Edition software, Quartus Embedded Edition software or select standalone tools may cause the software or tool to crash with an error similar to the crash signature shown below. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and v25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. Crash Signature: Error (22912): Unhandled exception: Fatal Error: Assertion failed tools/cpp/ddm/ddm_assessor.cpp:53: DDM_T::verify_token(token) : Cannot identify the client from function assertion_error in tools/cpp/ddm_report/ddm_report_msg.cpp@465 *** Fatal Error: Program termination requested *** *** Below is the stack trace at the time the error occurred. *** The lines beginning "Err Handler" represent frames relating *** to generating this report. *** The point at which the error occurred is somewhere after these lines. *** There may be a few frames representing standard/library code *** before the Quartus frames begin. *** The search for the error should begin with the Quartus frames. *** Unwinder: libunwind *** Stack depth: 15 Quartus 0x24e67: err_terminator() + 0x1bc (ccl_err) Quartus 0xb036a: __cxxabiv1::__terminate(void (*)()) + 0xa (stdc++) Quartus 0xb03d5: (stdc++) Quartus 0xb0628: (stdc++) Quartus 0x1680d: void ddm_throw<DDM_RUNTIME_ERROR>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x26d (ddm_report) Quartus 0x13fae: DDM_REPORT::DDM_ASSERTION_HANDLER::assertion_error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) const + 0xde (ddm_report) Quartus 0x12a52: DDM_REPORT::ASSERTION_HANDLER::error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) + 0x72 (ddm_report) Quartus 0x13e64: DDM_REPORT::detail::assert_at_line(char const*, char const*, int, char const*, ...) + 0x1b4 (ddm_report) Quartus 0x205fb0: ddm_set_lassessor(DDM_T_ASSESSOR*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x60 (ddm) Quartus 0xf4445: DMS_MANAGER::DMS_MANAGER() + 0x5c5 (dni_dms) Quartus 0xf45b2: DMS_MANAGER::get() + 0x7a (dni_dms) Quartus 0xf6db4: _GLOBAL__sub_I_dms_manager.cpp + 0x58 (dni_dms) Quartus 0x647e: (ld-linux-x86-64) Quartus 0x6568: (ld-linux-x86-64) Quartus 0x202ca: (ld-linux-x86-64) Resolution To work around this problem: For Windows machines Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Double click on the executable ending in “windows.exe”. When the GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch is installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Windows, use the following command: <patch_filename.exe> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer For Linux machines: Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Ensure you run chmod +x on the file ending with linux.run. Run in the command line: ./<installation_patch_run_file>. When GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run ./quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Linux, use the following command: ./<patch_filename.run> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer This issue is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. The below table lists the patches that are available and the associated patch number. The patch zip files are attached to the KDB below: Quartus Prime Pro Edition Version Patch Number 23.3 0.52 23.4 0.70 23.4.1 1.01 24.1 0.52 24.2 0.64 24.3 0.35 24.3.1 1.29 25.1 0.36 25.1.1 1.31 25.3 0.27 25.3.1 1.02
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPHow to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Linux shows "Cannot enable. Maybe the USB cable is bad?" error message when a USB 3.1 thumb-drive is plugged-in?
Description In Quartus® Prime software of version 25.3 and older, you may see the error message “Cannot enable. Maybe the USB cable is bad?” when a USB 3.1 thumb-drive is plugged-in. This is due to an incorrect Phase Locked-Loop Bandwidth configuration in PMA direct mode for USB, which caused the instability in USB 3.1 link layer when reaching the U0 state. This issue has been fixed in the newer Quartus® software releases. Resolution To solve this issue, upgrade your Quartus® software to Quartus® Prime Pro 25.3.1 version or newer versions.Why doesn’t Quartus® Prime Pro Edition Software version 25.3 generate programming files for my Agilex™ FPGA devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might not be able to generate programming files for some Agilex™ 5/3 FPGA devices. Here is the list of impacted OPNs: A5EG005BB18AE4S A5EG005BB18AE5S A5EG005BB18AE6S A5EG005BB18AE6X A5EG005BB18AI4S A5EG005BB18AI5S A5EG005BB18AI6S A5EG005BB18AI6X A5EG007BB18AE4S A5EG007BB18AE5S A5EG007BB18AE6S A5EG007BB18AE6X A5EG007BB18AI4S A5EG007BB18AI5S A5EG007BB18AI6S A5EG007BB18AI6X A3CZ025BB18AE7S A3CZ025BB18AI7S A3CZ050BB18AE7S A3CZ050BB18AI7S A3CZ065BB18AE7S A3CZ065BB18AI7S Resolution If you are using any of the listed devices in your design, download and install the patches below to enable programming file generation in Quartus® Prime Pro Edition Software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?
Description Due to a silicon problem in Agilex™ 5 and Agilex™ 3 devices, the SRS16 capability register of the SDMMC controller incorrectly reports in the EDS8 bit (bit 18) that the controller does not support the eMMC 8-bit bus width mode. As a result, the U-Boot eMMC driver identifies 4-bit mode as the maximum supported width and configures the controller accordingly. This occurs even if the bus-width parameter is explicitly set to 8 in the device tree. Resolution To work around this problem, use the sdhci-caps and sdhci-caps-mask parameters in the U-Boot device tree to override the incorrectly reported values in the capability registers (SRS16 and SRS17). For this case, override bit 18 in SRS16 to indicate that an 8-bit bus width is supported. Example configuration: &mmc { status = "okay"; bus-width = <8>; sdhci-caps = <0x00000000 0x00040000>; sdhci-caps-mask = <0x00000000 0x00040000>; sd-uhs-sdr50; cap-mmc-highspeed; bootph-all; }; Verification in U-Boot: After applying the workaround, you can verify that the controller is using an 8-bit bus width by running the mmc info command: SOCFPGA_AGILEX5 # mmc info Device: mmc0@10808000 Manufacturer ID: 13 OEM: 4e Name: G1M15L Bus Speed: 52000000 Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 29.6 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 29.6 GiB WRREL Boot Capacity: 31.5 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected This workaround will be permanently implemented in the Agilex™ 5/Agilex™ 3 U-Boot device tree in a future release of the FPGA HPS Embedded Software.Why True Differential input buffer with on-chip differential Termination (RD OCT) enabled does not respond after device is configured for Agilex™ 3 FPGA, Agilex™ 5 FPGA, and Agilex™ 7 FPGA devices?
Description The on-chip differential termination (RD OCT) for the True Differential input buffer is not enabled correctly in Quartus® Prime software. This issue impacts all True Differential Signaling (TDS) input buffer with RD OCT enabled, except when such input standard is used as the EMIF interface reference clock. Resolution This issue will be fixed progressively according to devices in the Quartus® Prime software. Refer to the tables below for the fix plan per device and Quartus® Prime version. Part Number Quartus® Prime v25.1 Quartus® Prime v25.1.1 Quartus® Prime v25.3 AGMxxxxxxxxxxVR0 Not Fixed Not Fixed Fixed AGMxxxxxxxxxxxVC Not Fixed Fixed Fixed A5Ex013xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex013xxxxxxxS/V/XCS/R1 A5Ex008xxxxxxxS/V/XCS/R1 Not Fixed Fixed Fixed A5Ex065xxxxxxxSR0 Not Fixed Not Fixed Fixed A5Ex065xxxxxxxS/V/E/X A5Ex052xxxxxxxS/V/E/X A5Ex043xxxxxxxS/V/E/X Not Fixed Not Fixed Fixed A3CxxxxxxxxxxxS Not Fixed Fixed Fixed Alternatively, you may use the below .tcl script to fix the differential termination settings in your .sof file manually. Please contact Altera Support team for assistance.Why does the HPS in Agilex™ 5 FPGA/Agilex™ 3 FPGA fail to load components from the QSPI device when the hardware design or SDM FW comes from Quartus® Prime Pro 25.1 and later?
Description Due to the QSPI Ownership Selection feature introduced in Quartus® Prime Pro 25.1, the HPS request for the ownership of the QSPI via the QSPI_DIRECT command can be either accepted or rejected by the SDM firmware. This request typically occurs during the FSBL stage, and the SDM firmware decides to reject or accept the request based on the QSPI Ownership setting defined in the hardware design. This affects scenarios such as Remote System Update (RSU), where the RSU components reside in the QSPI device, as well as any other boot flow that relies on the HPS loading components from QSPI, such as HPS booting from QSPI. The QSPI Ownership feature is not backward-compatible. Mixing .sof files generated from Quartus® Prime Pro versions prior to 25.1 with SDM firmware from 25.1 or later (and vice versa) may cause compatibility issues. This problem can also be observed when porting a hardware design from a Quartus® Prime Pro version prior to 25.1 to a newer version, because by default, Quartus® Pro assigns the QSPI ownership to the SDM. Resolution To avoid this problem, follow the recommendations provided below. In RSU scenarios, do not mix applications created with Quartus® Prime Pro versions prior 25.1 with applications created with 25.1 or later. Do not mix. .sof hardware designs created with Quartus® Prime Pro versions prior 25.1 with SDM FW from Quartus® Prime Pro 25.1 and later, and vice versa. In new hardware designs whose boot flow depends on the HPS loading components from the QSPI device or when porting these from Quartus® Prime Pro versions prior 25.1 to a more recent version, make sure to select the HPS as the QSPI owner in Quartus® configuration (from Assignments > Device > Device and Pin Options > QSPI Ownership configuration), because by default Quartus® assigns the QSPI ownership to SDM and missing this configuration will make HPS to fail to load these components. Additional Information For more information about this feature, you can refer to: A.2.2. HPS Use of SDM QSPI Controller Use Cases in n the Agilex5/Agilex 3 HPS Technical Reference Manual A.2.2.1. Feature Availability under SDM/HPS Ownership of Quad SPI Controller in n the Agilex5/Agilex 3 HPS Technical Reference Manual 4.2.1. Device and Pin Options in Agilex5/Agilex 3 HPS Booting User Guide 4.12. QSPI Controller Ownership Selection Impact on the HPS Software in Agilex5/Agilex 3 HPS Booting User Guide
