Knowledge Base Article

Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?

Description

Due to a silicon problem in Agilex™ 5 and Agilex™ 3 devices, the SRS16 capability register of the SDMMC controller incorrectly reports in the EDS8 bit (bit 18) that the controller does not support the eMMC 8-bit bus width mode.

As a result, the U-Boot eMMC driver identifies 4-bit mode as the maximum supported width and configures the controller accordingly. This occurs even if the bus-width parameter is explicitly set to 8 in the device tree.

Resolution

To work around this problem, use the sdhci-caps and sdhci-caps-mask parameters in the U-Boot device tree to override the incorrectly reported values in the capability registers (SRS16 and SRS17).

For this case, override bit 18 in SRS16 to indicate that an 8-bit bus width is supported. Example configuration:

&mmc {
       status = "okay";
       bus-width = <8>;
       sdhci-caps = <0x00000000 0x00040000>;
       sdhci-caps-mask = <0x00000000 0x00040000>;
       sd-uhs-sdr50;
       cap-mmc-highspeed;
       bootph-all;
};

 

Verification in U-Boot:

After applying the workaround, you can verify that the controller is using an 8-bit bus width by running the mmc info command:

 

SOCFPGA_AGILEX5 # mmc info
Device: mmc0@10808000
Manufacturer ID: 13
OEM: 4e
Name: G1M15L
Bus Speed: 52000000
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 29.6 GiB
Bus Width: 8-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 29.6 GiB WRREL
Boot Capacity: 31.5 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected

This workaround will be permanently implemented in the Agilex™ 5/Agilex™ 3 U-Boot device tree in a future release of the FPGA HPS Embedded Software.

Updated 6 days ago
Version 3.0
No CommentsBe the first to comment