Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the Multi-Channel DMA FPGA IP for PCI Express* stall or stop operating when the Q_SIZE parameter is configured to 0x10?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2 and later, the Multi-Channel DMA FPGA IP for PCI Express* may stall or cease operation when the Q_SIZE parameter is set to 0x10. Resolution The recommended workaround is to limit Q_SIZE to 0xF. If your design requires a Q_SIZE of 0x10, upgrade to the Quartus® Prime Pro Edition software version 25.3.1, regenerate the Multi-Channel DMA FPGA IP for PCI Express, and recompile the design to ensure the fix takes effect.How can I support legacy SFP modules with Agilex™ 7 FPGA F-Tile receivers?
Description Altera® Agilex™ 7 FPGA device F-Tile receivers cannot tolerate 2V pk-pk signals from legacy SFP modules. Resolution You can support legacy SFP modules by adding inline 6dB RF attenuators in between the SFP module and the Agilex™ 7 device F-Tile receiver. You must also power sequence the SFP module, ensuring that it powers up after the FPGA is configured. The Agilex™ 7 device F-Tile equalizer in Auto Adaptation mode should open the RX eye for reduced amplitude SFP+ signals.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Why o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy do I see multiple drivers to always_ff output variable errors in the Cadence Xcelium simulation for the Agilex™ 7 FPGA F-Tile PMA/FEC Direct PHY IP Example designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, you will see errors when you run Cadence Xcelium simulation on the F-Tile PMA/FEC Direct PHY IP Example Designs about multiple drivers to always_ff output variable. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.1.1, add below command in example_design/testbench/run_xcelium.sh: xmelab -warn_multiple_driver -relax -timescale '1 ps / 1 fs' -genhier -access +rwc top_tst This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.Why does the Design Closure Summary fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe the Design Assistant Summary flagged with High Severity Violations and Design Closure Summary marked as Fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs. These warnings can be safely ignored. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Warning(332174): Ignored filter at alt_sld_fab_0_st_dc_fifo_<unique ID>.sdc(Line number): *|in_wr_ptr_gray[*] could not be matched with a register
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see 'ignored filter' SDC warnings when your design includes the Partial Reconfiguration External Configuration Controller IP. Resolution This warning is safe to ignore and is scheduled to be removed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core Partial Reconfiguration External Configuration Controller IPWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).
