Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why isn’t a programming (SOF) file generated for the F-Tile Dynamic Reconfiguration Suite IP available for Example Designs when using the Quartus® Prime Pro Edition software versions 25.3 and earlier?
Description Due to starting from the Quartus® Prime Pro Edition software version 25.3 and earlier, it is compulsory to connect all the I/O ports to the correct PIN location. If any of the design I/O ports are floating and not properly connected, Quartus software will not be able to generate the programming file for the design compiled. This is mentioned in the Quartus Prime Pro Edition User Guide version 25.1.1 in 1.2. Generating Secondary Programming Files and provide the guidelines to the user on how to fix the Quartus software critical warning and successfully create the programming file for your design. Why don’t I get a programming file when I compile with the.... Similar programming (SOF) file generation problem you may observe when you generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting Target Development Kit with option 1) Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4xF-Tile) DK-SI-AGI027FA or 2) Agilex 7™ FPGA I-Series Transceiver-SoC Development Kit (Production 2 4xF-Tile) DK-SI-AGI027FC. As shown in the figure below. Resolution As a workaround, generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting the Target Development Kit with the option you want and compiling the design. Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternatively, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins. After adding any required assignments, recompile the design to generate a programming file. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the F-Tile Triple-Speed Ethernet IP Design Example fail during simulation on Windows using ModelSim* in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, the F-Tile Triple-Speed Ethernet (TSE) IP Design Example variant - “10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2xTBI PCS with F-Tile FGT Transceiver” - may fail during simulation on Windows platforms using ModelSim*. This problem occurs because the simulation script generated for the design example contains incorrect backslash (“\”) usage, which is not compatible with Windows* path formatting requirements. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software version 24.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why are there timing violations within the Triple-Speed Ethernet Intel® FPGA IP implemented on the F-Tile of Intel Agilex® 7 FPGA devices?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you may see timing violations on the following paths within the Triple-Speed Ethernet Intel® FPGA IP implemented on the F-Tile of Intel Agilex® 7 FPGA devices: From Node : i_ptp|eth_tse_0|i_tse_pcs_0|alt_mge_pcs20_inst|enc20|enc0|eout_dat[0] To Node : phymac_100g_ftile_auto_tiles|z1577a_x0_y166_n0|hdpldadapt_tx_chnl_23~pld_tx_clk1_dcm.reg From Node : phymac_100g_ftile_auto_tiles|z1577a_x0_y166_n0|hdpldadapt_rx_chnl_23~pld_rx_clk1_dcm.reg To Node : i_ptp|eth_tse_0|i_tse_pcs_0|alt_mge_pcs20_inst|rx_datain_reg_sc[5] Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.3. Download and install patch 0.25 from the following links: Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v22.3 Patch 0.25 (.txt) This issue has been fixed starting with Intel® Quartus® Prime Pro Edition Software version 22.4.Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.Why do the 10G and 25G example design SOF files generated for the E-tile Ethernet IP for Agilex™ 7 FPGAs with target development kit "Agilex™ 7 FPGA F-series Development Kit (Production 1 P-Tiles & E-tile)" fail to program?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may see failures when programming SOF files generated with the 10G and 25G E-Tile Ethernet Hard IP design examples for Agilex™ 7 FPGA devices. This issue applies to the E-Tile Ethernet Hard IP for Agilex™ 7 FPGA devices and is limited to the 10G and 25G Example Designs Resolution To workaround this problem, modify the PWRMGT_LINEAR_FORMAT_N setting to "-13" in the hardware test design QSF file located in <design_example_dir>/hardware_test_design. This problem is planned to be fixed in future versions of the Quartus® Prime Pro Software Edition.How can I erase all non-volatile memories of the Agilex™ 7 FPGA F-Series Development Kit?
Description The Agilex™ 7 FPGA F-Series Development Kit is populated with the following non-volatile memories which can be used for User Data: 8 GB eMMC NAND Flash Memory, Config QSPI 2GB Serial NOR Flash Memory, and MAX® 10 FPGA (MAX 10 USB BLASTER JTAG SW I2C CTRL) Other non-volatile memories are only used for configuration data, and they are not accessible for user data. Resolution To access and erase the Config QSPI 2GB Serial NOR Flash Memory and MAX® 10 FPGA (MAX 10 USB BLASTER JTAG SW I2C CTRL), you need to set the following configuration on SW4: SW4.1 = 0 SW4.2 = 0 SW4.3 = 1 SW4.4 = 0 To access and erase the 8GB eMMC NAND Flash Memory, it is required to boot the HPS, configure it and enable a routine to write/erase the eMMC. Contents or data can not be uploaded or downloaded from the eMMC without having the HPS booted and running. More information about the eMMC controller can be found in the Agilex™ Hard Processor System Technical Reference Manual chapter 16, SD/MMC Controller.When using the Intel Agilex® 7 FPGA P-Tile, why are simulation errors seen when compiling the Multi-Channel DMA Intel® FPGA IP for PCI Express testbench in the Cadence Xcelium simulator?
Description As stated in Table 34. Supported Simulators for MCDMA IP P-Tile of the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide, the Cadence Xcelium simulator is not supported if the simulation of this IP configuration is attempted using Cadence Xcelium, the following error will be seen: $>./xcelium_setup.sh ~~~~~ xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics. xmelab: *F,CUMSTS: Timescale directive missing on one or more modules. xmsim: 20.03-s005: (c) Copyright 1995-2020 Cadence Design Systems, Inc. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries. Resolution Support for the Cadence Xcelium simulator of this IP configuration is planned for a future release of the Intel® Quartus® Prime Pro Edition Software. To work around this problem with the existing IP release, please ensure a supported simulator is used.Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions?
Description Due to a compatibility problem between version 22.3 and later of the Intel® Quartus® Prime Software and the Siemens* QuestaSim* 2021.4, 2022.4 tool, simulation of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench will fail to simulation correctly with the following errors: # INFO: 116032 ns RP User Avmm Driver: begin RP Configuration. # FATAL: Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error! # FAILURE: Simulation stopped due to error! Resolution To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
