Why does the Synopsys VCS* simulator produce simulation errors with the F-Tile Ethernet Hard IP example design ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may see the following simulation errors with the F-Tile Ethernet Hard IP example design. ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd0, ReaddataValid = 1, Readdata = 01010142, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd4, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd8, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fdc, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; The readdata values of these cwbin counter registers are expected values. The errors are due to wrong check tasks in testbench. Resolution Users can safely ignore these mismatching errors. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP.Why doesn’t the F-Tile Debug Toolkit in the F-Tile Avalon® Streaming IP for PCI Express* report error work in the Quartus® Prime Pro Edition Software v21.4 ?
Description Due to problems in the F-Tile Debug Toolkit in the Quartus® Prime Pro Edition Software v21.4, the F-Tile Debug Toolkit does not run when F-Tile is configured in 1 x4 endpoint mode. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. A patch is available to fix this problem for the Quartus Prime Pro Edition Software version 21.4. Download and install Patch 0.19 below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.1.Why does the F-tile Serial Lite IV IP Design Example fail?
Description Due to a problem in the Clock Controller GUI of the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, the F-tile Serial Lite IV IP Design Example fails when you need to configure the OUT1 clock frequency of the chip Si5332. This is because there is a problem with this Si5332 GUI; the OUT1 frequency can not be accurately configured. Similar failures might be seen for all Agilex™ 7 F-tile IP designs if you use the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, your design utilizes the Si5332 OUT1 clock, and the default frequency, 166.66 MHz, needs to be changed. Resolution To work around this problem, you should avoid setting the Si5332 OUT1 frequency directly using the "set" button. You need to use the "import" button to accurately set the Si5332 OUT1 clock frequency. ClockBuilder Pro software can export the import function of a TXT file. A sample si5332 project and a si5332-project.txt file are attached for reference. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Which Fast Simulation Macros are documented for the Agilex™ 7 FPGA F-Tile Hard IP?
Description This KDB details the recent advancements in macro development to improve simulation speeds for the Agilex™ 7 FPGA F-Tile Ethernet IPs. Its purpose is to clarify the specific macros applicable to various IPs and their compatibility with different versions of the Quartus® Prime Pro Edition Software. Other Macros already detailed in existing documentation, ip scripts or design examples should continue to be used as is. In any other circumstance, you should not pro-actively add them to your design. Resolution Refer to the attached document. This document provides an extensive overview, showing the macros applicable to each IP. This will help you quickly identify the appropriate macro for your simulation needs.Why are the configuration pin names in the Quartus® Prime Pro Edition Software v21.2 different to the User Guides and Pin Connection Guidelines?
Description Due to a problem in the Quartus® Prime Pro Edition Software v21.2, you will see SDMMC_CFG* pin names instead of AS_nRST and PWRMGT_ALERT pin names when targeting the following Agilex™ 7 FPGA F-Series devices: AGFA014/AGFB014 (R24A) AGFA012/AGFB012 (R24A) AGFA022/AGFB022 (R25A) AGFA027/AGFB027 (R25A) You will see that the following documentation have replaced the SDMMC_CFG* pin names with AS_nRST and PWRMGT_ALERT pin names for Agilex™ FPGA F-Series devices: Agilex™ 7 FPGA Configuration User Guide Agilex™ FPGA Power Management User Guide Agilex™ 7 FPGA Device Family Pin Connection Guidelines Agilex™ FPGA Device Pin-Out Files Resolution A patch 0.27 is available to fix this problem for the Quartus® Prime Pro Edition Software v21.2. Please download and install the patch below. This problem is fixed starting with the Quartus® Prime Pro Edition Software v21.3.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does configuration intermittently fail when using a JIC file generated with Quartus® Prime Pro Edition version 24.2 and later on Agilex™ 7 FPGA devices, resulting in Major Error Code 0x0000F004 and Minor Error Code 0x0000D006?
Description You may encounter the following errors during configuration using a JIC file generated with Quartus® Prime Pro Edition version 24.2 and later, targeting Agilex™ 7 FPGA devices with F-tile and/or R-tile: Major Error code: 0x0000F004; Minor Error Code: 0x0000D006; This issue affects configuration behavior on Agilex™ 7 FPGA devices with F-tile and/or R-tile. Resolution To work around this issue: Power cycle the FPGA. Note: Triggering nCONFIG will not resolve the issue. Patches are also available to fix this problem for the following Quartus® Prime Pro version: 24.2: Quartus Prime Pro Edition Design Software v24.2 patch 0.59fw 25.1: Quartus Prime Pro Edition Design Software v25.1 patch 0.25fw This problem is fixed starting from Quartus® Prime Pro Edition version 25.1.1 and later.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*
