What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?

Description

To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz.

Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash.

For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only.

Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide

Related IP Cores

• F-Tile Avalon® Streaming IP for PCI Express*
• Multi Channel DMA FPGA IP for PCI Express*
• P-Tile Avalon® Streaming IP for PCI Express*
• R-Tile Avalon® Streaming IP for PCI Express*
• AXI Streaming IP for PCI Express*
• AXI Multichannel DMA IP for PCIe*